Method for aligning backside pattern based on one or more frontside alignment marks of a semiconductor wafer
AssigneeAlpha and Omega Semiconductor International LP
InventorsJian Wang, Lei Zhang, Changqing Zhan, Tai-Ming Lin
Life of this patent
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Abstract
A method comprises the steps of providing a semiconductor wafer comprising a substrate layer; forming a first alignment mark and a second alignment mark; forming a plurality of super junction buffer regions; forming additional two or more epitaxial layers; forming additional one or more alignment marks; forming a top layer; thinning the wafer; forming a first plurality of regions and a second plurality of regions; and applying a singulation process. Devices made by the method have reduced misalignment, between a top portion and a bottom portion of an interface within the devices, for less than 0.5 micron.
Claims12
A method for fabricating a plurality of semiconductor devices, the method comprising the steps of:
- providing a semiconductor wafer comprising:
- a substrate layer being a doped first conductivity type silicon substrate layer, the substrate layer comprising a first side and a second side opposite the first side;
- forming an epitaxial layer on the first side of the substrate layer, the epitaxial layer comprising a first side and a second side opposite the first side, the second side of the epitaxial layer being attached to the first side of the substrate layer;
- forming a first alignment mark and a second alignment mark on the first side of the epitaxial layer;
- forming a photoresist pattern on the first side of the epitaxial layer;
- forming a plurality of super junction buffer regions on the first side of the epitaxial layer;
- removing the photoresist pattern;
- forming additional two or more epitaxial layers, the additional two or more epitaxial layers comprising a first side and a second side opposite the first side, the second side of the additional two or more epitaxial layers being attached to the first side of the epitaxial layer;
- forming a first refreshed alignment mark, a second refreshed alignment mark, and additional one or more alignment marks on the first side of the additional two or more epitaxial layers, a distance between a center of the wafer and a first one of the additional one or more alignment marks is in a range from twenty percent to seventy percent of a radius of the wafer;
- forming a top layer;
- removing the substrate layer;
- applying a grinding process to the second side of the epitaxial layer forming a thinned epitaxial layer comprising an exposed surface;
- forming a first plurality of regions and a second plurality of regions on the exposed surface of the thinned epitaxial layer by referencing the additional one or more alignment marks;
- and
- applying a singulation process forming the plurality of semiconductor devices.
Dependencies are inferred from the claim text.