Techniques for protecting integrated circuitry from plasma-induced electrostatic discharge using a carrier substrate with junction features

An electronic device, comprising:

• a chip package comprising one or more dies, at least one of the one or more dies comprising
• a plurality of semiconductor devices having source and drain regions on a semiconductor substrate, the semiconductor substrate having a first doped region separate from the source and drain regions;
• a conductive layer in the semiconductor substrate, the conductive layer abutting the first doped region in the semiconductor substrate;
• an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers;
• one or more metal features in any of the plurality of stacked interconnect layers;
• one or more conductive vias through one or more layers of the interconnect region and coupled to any of the one or more metal features;
• and
• a carrier substrate having a semiconductor material with one or more second doped regions and one or more conductive pads in physical contact with corresponding ones of the one or more second doped regions, wherein the carrier substrate is bonded to the interconnect region such that the one or more conductive pads are in contact with corresponding ones of the one or more conductive vias.

An integrated circuit comprising:

• a plurality of semiconductor devices on a first substrate, the first substrate having a semiconductor material with one or more first doped regions beneath the plurality of semiconductor devices;
• one or more conductive layers in the first substrate and physically contacting corresponding ones of the one or more first doped regions;
• an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers;
• one or more metal features in any of the plurality of stacked interconnect layers;
• one or more conductive structures that extend between the one or more conductive layers and one or more of the metal features in the interconnect region;
• one or more conductive vias through one or more layers of the interconnect region and coupled to any of the one or more metal features;
• and
• a second substrate having a semiconductor material with one or more second doped junctions and one or more conductive pads in physical contact with corresponding ones of the one or more second doped junctions, wherein the second substrate is bonded to the interconnect region such that the one or more conductive pads are in contact with corresponding ones of the one or more conductive vias.