Direct backside contact with replacement backside dielectric
AssigneeInternational Business Machines Corporation
InventorsRuilong Xie, Kisik Choi, Son Nguyen, Nicholas Alexander Polomoff
Life of this patent
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Abstract
A semiconductor device includes a frontside including first metal structures, transistors disposed between the frontside and a backside opposite the frontside, each transistor including a source/drain positioned within a stack of nanolayers, the stack of nanolayers forming a gate structure and a power circuit on the backside and connected to the transistors by backside contacts. A backside dielectric isolation has a horizontal portion along a backside of the gate structure and a vertical portion substantially perpendicular to the backside and self-aligned to selected source/drains to electrically isolate the power circuit from the transistors.
Claims20
A method of forming a semiconductor device, comprising:
- forming recesses through a stack of nanolayers from a frontside opposite a substrate to a buried semiconductor layer through an intermediate semiconductor layer;
- filling a portion of the recesses to a height relative to the stack of nanolayers to form a sacrificial plug within the recesses;
- forming a source/drain on the plug within the recesses;
- removing the substrate, the intermediate semiconductor layer and the buried semiconductor layer to expose plugs in the recesses from a backside opposite the frontside;
- burying the plugs that were exposed in a first dielectric material;
- removing the plugs and a lowest nanolayer in the stack of nanolayers to form a cavity;
- and
- filling the cavity with a second dielectric material to form backside dielectric isolation to electrically isolate a transistor formed in a region of the stack of nanolayers from a power circuit on the backside.
A semiconductor device,
- comprising:
- a frontside including first metal structures;
- transistors disposed between the frontside and a backside opposite the frontside, each transistor including a source/drain positioned within a stack of nanolayers, the stack of nanolayers forming a gate structure;
- a power circuit on the backside and connected to the transistors by backside contacts;
- and
- a backside dielectric isolation having a horizontal portion along a backside of the gate structure and a vertical portion substantially perpendicular to the backside and self-aligned to selected source/drains to electrically isolate the power circuit from the transistors, wherein the horizontal portion directly contacts at least one gate metal of the transistors.
A semiconductor device,
- comprising:
- a frontside including first metal structures;
- transistors disposed between the frontside and a backside opposite the frontside, each transistor including source/drains positioned within a stack of nanolayers, the stack of nanolayers forming a gate structure;
- a backside power rail on a backside power delivery network (BSPDN);
- a backside interlevel dielectric layer on the backside power rail and the BSPDN;
- and
- a backside dielectric isolation adjacent to and passing through the backside interlevel dielectric layer, the backside dielectric isolation having a horizontal portion along a backside of the gate structure and a vertical portion substantially perpendicular to the backside and self-aligned to selected source/drains to electrically isolate a power circuit from the transistors.
Dependencies are inferred from the claim text.