Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device, the method comprising:

• (a) preparing a semiconductor substate having a first chip region, a second chip region, and a scribing region that is provided between the first and second chip regions and extends in a first direction in a plan view;
• (b) forming a first conductor pattern via a first insulating film on the semiconductor substate of the scribing region;
• (c) forming a second insulating film covering the first conductor pattern;
• (d) forming a plurality of holes in the second insulating film so as to be located on the first conductor pattern;
• (e) forming a plurality of second conductor patterns connected to the first conductor pattern in the plurality of holes;
• (f) forming a third conductor pattern connected to the plurality of second conductor patterns on the second insulating film and on the plurality of second conductor patterns;
• and
• (g) cutting off the scribing region along the first direction by using a dicing blade so that a part of the scribing region is left in each outer periphery of the first chip region and the second chip region,
• wherein, in a second direction intersecting with the first direction as a plan view, a width of the dicing blade is narrower than a width of the first conductor pattern and a width of the third conductor pattern before the (g),
• wherein, after the (g), a part of the first conductor pattern, all or a part of at least one of the plurality of second conductor patterns, and a part of the third conductor pattern are left in each of the scribing region on a side of the first chip region and the scribing region on a side of the second chip region,
• wherein the (b) includes:
• (b1) forming a trench in the semiconductor substrate of each of the first chip region and the second chip region;
• (b2) forming the first insulating film in the trench and on the semiconductor substrate within the first chip region, in the trench and on the semiconductor substrate within the second chip region, and on the semiconductor substrate within the scribing region;
• (b3) forming a polycrystalline silicon film on the first insulating film;
• and
• (b4) selectively pattering the polycrystalline silicon film, thereby forming, in the first chip region and the second chip region, a gate electrode embedded in the trench, and a resistance element formed on the semiconductor substrate and separated from the gate electrode, and forming the first conductor pattern on the semiconductor substrate in the scribing region,
• wherein, in the (c), the second insulating film is formed in the first chip region and the second chip region so as to cover the gate electrode and the resistance element,
• wherein, in the (d), a via-hole is formed in the second insulating film within the first chip region and the second chip region so as to be located on the gate electrode,
• wherein, in the (e), a via connected to the gate electrode is formed in the via-hole within the first chip region and the second chip region, and
• wherein, in the (f), a gate wing connected to the via is formed on the second insulating film and on the via within the first chip region and the second chip region.

A method of manufacturing a semiconductor device, the method comprising:

• (a) preparing a semiconductor substrate with a first conductivity type, the semiconductor substrate having a first chip region, a second chip region, and a scribing region that is provided between the first chip region and the second chip region and extends in a first direction in a plan view;
• (b) forming a seventh conductor pattern in the semiconductor substrate of the scribing region, the seventh conductor pattern having a second conductivity type opposite to the first conductivity type;
• (c) forming a second insulating film so as to cover the seventh conductor pattern;
• (d) forming a plurality of holes in the second insulating film so as to be located on the seventh conductor pattern;
• (e) forming, in the plurality of holes, a plurality of second conductor patterns connected to the seventh conductor pattern;
• (f) forming, on the second insulating film and the plurality of second conductor patterns, a third conductor pattern connected to the plurality of second conductor patterns;
• and
• (g) using a dicing blade to cut off the scribing region along the first direction so that a part of the scribing region is left on an outer periphery of each of the first chip region and the second chip region,
• wherein, in a second direction intersecting with the first direction in a plan view, a width of the dicing blade is narrower than a width of the seventh conductor pattern and a width of the third conductor pattern before the (g), and
• wherein, after the (g), a part of the seventh conductor pattern, at least one of the plurality of second conductor patterns, and a part of the third conductor pattern are left in each of the scribing region on a side of the first chip region and the scribing region on a side of the second chip region.