Semiconductor package and method for manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHyunsoo Chung, Dae-Woo Kim, Young Lyong Kim, Inhyo Hwang
Life of this patent
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Abstract
A semiconductor package according to at least one embodiment may include: a first chiplet and a second chiplet disposed side by side with each other, wherein each of the first chiplet and the second comprises a substrate including an active side and a back side opposite to the active side; a back side power distribution network (BSPDN) in the back side of the substrate; and a third chiplet electrically coupling the first chiplet and the second chiplet to each other above the first chiplet and the second chiplet; and a fourth chiplet and a fifth chiplet disposed side by side with the third chiplet.
Claims20
A semiconductor package comprising:
- a first chiplet including a first substrate including a first active side and a first back side opposite to the first active side, the first back side of the first substrate including a first back side power distribution network (BSPDN);
- a second chiplet including a second substrate including a second active side and a second back side opposite to the second active side, the second back side of the second substrate including a second BSPDN, wherein the first substrate and the second substrate are side by side with each other;
- a third chiplet above the first chiplet and the second chiplet and electrically coupling the first chiplet and the second chiplet to each other;
- and
- a fourth chiplet and a fifth chiplet side by side with the third chiplet.
A semiconductor package comprising:
- a redistribution layer substrate;
- a first chiplet and a second chiplet above the redistribution layer substrate and side by side with each other, wherein each of the first chiplet and the second chiplet includes a back side power distribution network (BSPDN);
- a first redistribution layer structure on the first chiplet;
- a second redistribution layer structure on the second chiplet;
- a third chiplet above the first chiplet and the second chiplet, and overlapping with a partial region of the first redistribution layer structure and a partial region of the second redistribution layer structure, the third chiplet configured to electrically couple the first redistribution layer structure and the second redistribution layer structure;
- and
- a fourth chiplet and a fifth chiplet side by side with the third chiplet.
A method for manufacturing a semiconductor package, comprising:
- forming a first chiplet and a second chiplet, wherein the first chiplet and the second chiplet include a back side power distribution network (BSPDN);
- forming a first redistribution layer structure on the first chiplet;
- forming a second redistribution layer structure on the second chiplet;
- mounting the first chiplet and the second chiplet on a redistribution layer substrate;
- mounting a third chiplet above the first redistribution layer structure and the second redistribution layer structure such that the third chiplet overlaps on a partial region of the first redistribution layer structure and a partial region of the second redistribution layer structure and electrically couples the first redistribution layer structure and the second redistribution layer structure;
- mounting a fourth chiplet on the first redistribution layer structure and a fifth chiplet on the second redistribution layer structure such that the fourth chiplet and the fifth chiplet are side by side with the third chiplet;
- and
- molding the first redistribution layer structure, the second redistribution layer structure, the first chiplet, the second chiplet, the third chiplet, the fourth chiplet, and the fifth chiplet on the redistribution layer substrate.
Dependencies are inferred from the claim text.