Integrated circuit device

An integrated circuit device comprising:

• a substrate having a back side surface;
• a plurality of fin-type active regions protruding from the substrate to define a plurality of trench regions in the substrate on an opposite side of the back side surface, the plurality of fin-type active regions extending in a first lateral direction;
• a plurality of source/drain regions on the plurality of fin-type active regions, respectively;
• a device isolation film covering a portion of a sidewall of each of the plurality of fin-type active regions in the plurality of trench regions, the device isolation film apart from the substrate in a vertical direction;
• an inter-gate dielectric film on the device isolation film and surrounding the plurality of source/drain regions;
• a plurality of etch stop structures between the substrate and the device isolation film at bottoms of the plurality of trench regions, respectively;
• a via power rail apart from the plurality of fin-type active regions and the plurality of source/drain regions in a lateral direction, in the vertical direction the via power rail passing through a portion of one selected etch stop structure selected from the plurality of etch stop structures;
• and
• a backside power rail passing from the back side surface of the substrate through the substrate in the vertical direction and passing through another portion of the one selected etch stop structure in the vertical direction, the backside power rail being in contact with one end of the via power rail.

An integrated circuit device comprising:

• a substrate having a back side surface;
• a fin-type active region protruding from the substrate to define a portion of a trench region in the substrate on an opposite side of the back side surface;
• at least one nanosheet on the fin-type active region, the at least one nanosheet apart from a fin top surface of the fin-type active region in a vertical direction;
• a gate line surrounding the at least one nanosheet on the fin-type active region, the gate line extending in a second lateral direction, the second lateral direction intersecting a first lateral direction;
• a source/drain region adjacent to the gate line on the fin-type active region, the source/drain region in contact with the at least one nanosheet;
• a device isolation film covering at least a portion of a sidewall of the fin-type active region in the trench region, the device isolation film apart from the substrate in the vertical direction;
• an etch stop structure comprising an insulating liner and an insulating stopper, the insulating liner filling at least a portion of the trench region between the substrate and the device isolation film, the insulating liner being in contact with each of the sidewall of the fin-type active region and the substrate, and the insulating stopper between the insulating liner and the device isolation film;
• a via power rail apart from each of the fin-type active region, the source/drain region, and the gate line in the second lateral direction, the via power rail passing through the gate line in the vertical direction and passing through at least a portion of the etch stop structure;
• and
• a backside power rail passing from the back side surface of the substrate through the substrate in the vertical direction and contacting one end of the via power rail.