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US 12,721,126 B2Granted
Semiconductor device and method of manufacture
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYao-Wen Hsu, Ming-Che Ku, Neng-Jye Yang, Yu-Wen Wang
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Abstract
An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.
Claims20
A method of manufacturing a semiconductor device, the method comprising:
- forming a first conductive element and a second conductive element within a substrate, the second conductive element separated from the first conductive element;
- forming a first dielectric etch stop layer overlying and in physical contact with the first conductive element;
- forming a low-k dielectric layer over the first dielectric etch stop layer;
- forming a plurality of openings extending through the first dielectric etch stop layer and the low-k dielectric layer, wherein each of the plurality of openings exposes a conductive element, wherein at least two of the plurality of openings expose the first conductive element, and at least one of the plurality of openings exposes the second conductive element, wherein an active device is electrically connected to the second conductive element;
- reducing a surface potential difference between the first conductive element and the second conductive element by applying a first treatment chemical that is both volatile and has a low conductivity;
- and
- filling the plurality of openings with a conductive material and planarizing the conductive material, wherein after the filling the conductive material extends through the first dielectric etch stop layer only through the plurality of openings and wherein the filling is continuous from a time when the first conductive element and the second conductive element are exposed to a time when the conductive material is continuous as it extends from the first conductive element to the second conductive element, wherein the conductive material remains continuous after the planarizing as it extends from the first conductive element to the second conductive element.
4 more elements
A semiconductor device comprising:
- an active device at least partially located within a substrate;
- a first conductive element located within a dielectric layer, the first conductive element electrically connected to the active device;
- a second conductive element located within the dielectric layer, the second conductive element separated from the first conductive element;
- a first etch stop layer over and in physical contact with both the first conductive element and the second conductive element;
- a low-k dielectric layer overlying the first etch stop layer;
- a first conductive via extending through the first etch stop layer and the low-k dielectric layer, the first conductive via in physical contact with the first conductive element;
- a second conductive via extending through the first etch stop layer and the low-k dielectric layer, the second conductive via in physical contact with the second conductive element;
- a third conductive via extending through the first etch stop layer and the low-k dielectric layer, the third conductive via in physical contact with the second conductive element, the third conductive via separated from the second conductive via by at least a portion of the low-k dielectric layer;
- and
- a conductive material extending over the low-k dielectric layer and in physical contact with all of the first conductive via, the second conductive via and the third conductive via, wherein each conductive via extending away from the conductive material through the first etch stop layer makes physical contact with one of a plurality of conductive structures, the plurality of conductive structures comprising the first conductive element and the second conductive element, the conductive material being continuous as the conductive material extends from being in physical contact with the first conductive via to being in physical contact with the second conductive via and the third conductive via.
7 more elements
A method of manufacturing a semiconductor device, the method comprising:
- forming a first conductive element embedded within a dielectric layer and in electrical connection with an active device;
- forming a second conductive element embedded within the dielectric layer;
- reducing a surface potential difference between the first conductive element and the second conductive element, wherein the reducing further comprises applying a first treatment chemical, the first treatment chemical being volatile and having a low conductivity;
- forming a first via surrounded by a first etch stop layer and a low-k dielectric layer;
- forming a second via surrounded by the first etch stop layer and the low-k dielectric layer;
- forming a third via surrounded by the first etch stop layer and the low-k dielectric layer, wherein after the forming the third via, the first conductive element is in physical contact with the first via, and wherein the second conductive element is in physical contact with both the second via and the third via, and wherein each via located through the low-k dielectric layer and electrically connected to the active device is in physical contact with at least one of either the first conductive element or the second conductive element;
- forming a conductive material using a same process as the first via, the second via, and the third via, the conductive material extending continuously from a position over the first via to a position over the third via;
- and
- planarizing the conductive material until the conductive material is planar with a second dielectric layer different from the low-k dielectric layer.
6 more elements
Dependencies are inferred from the claim text.