Semiconductor device and method

A method comprising:

• depositing a first sacrificial layer and a first channel layer sequentially over a semiconductor substrate;
• patterning the first sacrificial layer, the first channel layer, and the semiconductor substrate to form a fin structure that protrudes from the semiconductor substrate;
• forming isolation regions on opposite sides of the fin structure, wherein the fin structure protrudes above top surfaces of the isolation regions;
• forming a first source/drain region in the fin structure, the first source/drain region extending through the first sacrificial layer and the first channel layer;
• forming an insulating fin that extends into the fin structure and isolates a first portion of the fin structure from a second portion of the fin structure;
• forming a metal-semiconductor alloy region over the first source/drain region;
• forming a coating layer over the metal-semiconductor alloy region, wherein during forming the coating layer and the metal-semiconductor alloy region, a residual layer is formed on a top surface of the insulating fin, and top surfaces of the isolation regions;
• and
• performing a wet etching process to selectively etch the residual layer from the top surface of the insulating fin and the top surfaces of the isolation regions.

A method comprising:

• forming a fin structure protruding from a semiconductor substrate, the fin structure comprising alternating semiconductor nanostructures and sacrificial nanostructures;
• forming isolation regions on opposite sides of the fin structure, wherein the fin structure protrudes above top surfaces of the isolation regions;
• forming a dummy gate stack over a top surface and sidewall of the fin structure;
• forming a first source/drain region in the fin structure, the first source/drain region extending through the semiconductor nanostructures and the sacrificial nanostructures;
• forming a first spacer adjacent to the dummy gate stack, wherein the first spacer is disposed over a top surface of the first source/drain region;
• forming a metal-semiconductor alloy region over the first source/drain region;
• and
• forming a coating layer over the metal-semiconductor alloy region, wherein during forming the coating layer and the metal-semiconductor alloy region, a residual layer is formed on a sidewall of the first spacer, and the top surfaces of the isolation regions.