Vacuum packaging manufacturing method and semiconductor devices manufactured thereby

Abstract

A vacuum packaging manufacturing method includes forming, on a silicon wafer, a lower layer including a first metal layer and a second metal layer formed on the first metal layer, forming anchor regions by etching parts of the second metal layer and depositing a dielectric layer on the second metal layer in which the anchor regions are formed, exposing a silicon oxide film by removing a partial region of the dielectric layer and removing silicon oxide inside the second metal layer covered by the dielectric layer through the removed partial region of the dielectric layer, and depositing an upper layer on the second metal layer and forming a third metal structure on the upper layer, wherein, as the upper layer is deposited on the second metal layer, a region from which the silicon oxide inside the second metal layer is removed is in a vacuum or subvacuum state.

Dependencies are inferred from the claim text.