Phase-change random access memory device and methods of making the same

A memory array comprising:

• transistors disposed on a substrate;
• word lines electrically connected to gate electrodes of the transistors;
• source lines electrically connected to source regions of the transistors;
• memory cells disposed over the transistors;
• contact features CO electrically connecting drain regions 36 of the transistors to bottom electrodes of the memory cells;
• and
• bit lines electrically connected to top electrode of the memory cells,
• wherein:
• the memory cells each comprise a phase-change layer disposed between the top electrode and bottom electrode and comprising a chalcogenide germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) material;
• a Ge content of the phase change layer varies by from about 10 at % to about 30 at %, in a thickness direction extending from the top electrode to the bottom electrode;
• and
• the phase change layer has a minimum Ge content of at least 30 at %.

A memory device comprising:

• a bottom electrode;
• a top electrode disposed over the bottom electrode;
• and
• a phase-change layer disposed on the bottom electrode and comprising a chalcogenide germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) material;
• a barrier electrode disposed on the phase-change layer;
• a selector layer disposed on the barrier electrode;
• and
• a top electrode disposed on the selector layer,
• wherein:
• a Ge content of the phase change layer varies by from about 10 at % to about 30 at %, in a thickness direction extending from the top electrode to the bottom electrode;
• and
• the phase change layer has a minimum Ge content of at least 30 at %.