US 12,720,903 B1Granted

Integrated active silicon photonic devices and methods thereof

AssigneeAeluma, Inc.

InventorsBei Shi, Bowen Song, Jonathan Klamkin

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Abstract

Integrated systems including photonic integrated circuit (PIC) devices and methods of fabrication using selective area heteroepitaxy (SAH). The methods include forming a plurality of waveguide structures overlying a substrate, forming a cavity region between the waveguide structures, and forming a plurality of device materials within the cavity region such that an active region material of these device materials is aligned to at least a portion of the waveguide structures. The plurality of device materials can include compound semiconductor (CS) materials deposited by SAH, can be coupled to the waveguide structures or configured with an interface region in between, and can form an optical device, a laser device, or the like. Further, the resulting device can be integrated with other devices formed by SAH in separate cavity regions. The devices in the integrated system can be configured in a coupling scheme, such as a butt-coupling, directional coupling, or the like.

Claims34

Dependent claims

A method of fabricating an integrated system having a photonic integrated circuit (PIC) device, the method comprising:

providing a partially completed semiconductor wafer comprising a substrate, a first insulating layer overlying the substrate, and a device layer overlying the first insulating layer;
removing one or more portions of the device layer to form a plurality of waveguide structures overlying the first insulating layer;
forming a second insulating layer overlying the plurality of waveguide structures and the first insulating layer;
subjecting the second insulating layer to polishing process;
removing one or more portions of the second insulating layer, the first insulating layer, and the substrate to form a plurality of cavity regions, each exposing a recessed surfaced region of the substrate;
forming a thin conformal insulating layer overlying the second insulating layer and the cavity regions;
removing one or more portions of the thin conformal insulating layer overlying the second insulating material and the recessed surface regions of the substrate to form a sidewall spacer material within each cavity region;
subjecting the recessed surface regions of the substrate to a surface preparation process;
forming a buffer material overlying the recessed surface region within each cavity region;
forming an active photonic device within a first cavity region of the plurality of cavity regions, the forming of the active photonic device including forming a plurality of device materials within the first cavity region overlying the recessed surface region of the substrate within the first cavity region using a selective area heteroepitaxy (SAH) process, wherein forming the plurality of device materials comprises
forming an n-type contact material overlying the buffer material within the first cavity region;
forming an n-type lower cladding material overlying the n-type contact material;
forming an active region material overlying the n-type cladding material, wherein the active region material is aligned with at least a portion of the plurality of waveguide structures;
forming a p-type upper cladding material overlying the active region material;
and
forming a p-type contact material overlying the p-type upper cladding material;
forming a photonic device in each of the remaining cavity regions using an SAH process;
wherein forming each such photonic device includes forming a second thin insulating layer overlying the plurality of cavity regions and all previously formed photonic devices, removing a portion of the second thin insulating layer within a target cavity region, and forming one or more photonic device materials overlying the buffer material within the target cavity region using an SAH process;
forming a third insulating layer overlying the plurality of cavity regions, the active photonic device, the photonic devices, and the second thin insulating layers;
and
planarizing the third insulating layer.

18 more elements

A method of fabricating an integrated system having a photonic integrated circuit (PIC) device, the method comprising:

providing a substrate;
forming a first insulating layer overlying the substrate;
removing a plurality of portions from the first insulating layer to form a plurality of trenches, each of which exposes a portion of the substrate,
removing a plurality of portions from the substrate to form a plurality of v-grooves within the substrate using the plurality of trenches;
removing the remaining portions of the first insulating layer;
forming a second insulating layer overlying the substrate;
forming a multi-layer device stack overlying the second insulating layer, the multi-layer device stack having at least a first device layer overlying the second insulating layer, a first device cladding layer overlying the first device layer, and a second device layer overlying the first cladding layer;
removing one or more portions of the multi-layer device stack to form a plurality of waveguide structures overlying the second insulating layer;
forming a third insulating layer overlying the plurality of waveguide structures and the second insulating layer;
removing one or more portions of the third insulating layer and the second insulating layer to form a plurality of cavity regions, each exposing a surface region of the substrate;
forming a buffer material overlying the exposed surface region of the substrate within each cavity region;
forming an active photonic device within a first cavity region of the plurality of cavity regions, the forming of the active photonic device including forming a plurality of device materials within the first cavity region overlying the surface region of the substrate within the first cavity region using a selective area heteroepitaxy (SAH) process, wherein forming the plurality of device materials comprises
forming an n-type contact material overlying the buffer material within the first cavity region;
forming an n-type lower cladding material overlying the n-type contact material;
forming an active region material overlying the n-type cladding material, wherein the active region material is aligned with at least a portion of the plurality of waveguide structures;
forming a p-type upper cladding material overlying the active region material;
and
forming a p-type contact material overlying the p-type upper cladding material;
forming a photonic device in each of the remaining cavity regions using an SAH process;
wherein forming each such photonic device includes forming a thin insulating layer overlying the plurality of cavity regions and all previously formed photonic devices, removing a portion of the thin insulating layer within a target cavity region, and forming one or more photonic device materials overlying the buffer material within the target cavity region using an SAH process;
forming a fourth insulating layer overlying the plurality of cavity regions, the active photonic device, the photonic devices, and the thin insulating layers;
and
planarizing the fourth insulating layer.

20 more elements

A method of fabricating an integrated system having a photonic integrated circuit (PIC) device, the method comprising:

providing a substrate;
forming a first insulating layer overlying the substrate;
forming a multi-layer device stack overlying the second insulating layer, the multi-layer device stack having at least a first device layer overlying the second insulating layer, a first device cladding layer overlying the first device layer, and a second device layer overlying the first cladding layer;
removing one or more portions of the multi-layer device stack to form a plurality of waveguide structures overlying the first insulating layer;
forming a second insulating layer overlying the plurality of waveguide structures and the first insulating layer;
removing a first plurality of portions from the second insulating layer and the first insulating layer using a high aspect ratio etching process to form a plurality of trenches, each of the trenches exposing a portion of a surface region of the substrate;
removing a plurality of portions from the substrate to form a plurality of v-grooves within the substrate using the plurality of trenches;
removing a second plurality of portions from the second insulating layer and the first insulating layer to form a plurality of cavity regions, each exposing the surface region of the substrate;
forming a buffer material overlying the exposed surface region of the substrate within each cavity region;
forming an active photonic device within a first cavity region of the plurality of cavity regions, the forming of the active photonic device including forming a plurality of device materials within the first cavity region overlying the surface region of the substrate within the first cavity region using a selective area heteroepitaxy (SAH) process, wherein forming the plurality of device materials comprises
forming an n-type contact material overlying the buffer material within the first cavity region;
forming an n-type lower cladding material overlying the n-type contact material;
forming an active region material overlying the n-type cladding material, wherein the active region material is aligned with at least a portion of the plurality of waveguide structures;
forming a p-type upper cladding material overlying the active region material;
and
forming a p-type contact material overlying the p-type upper cladding material;
forming a photonic device in each of the remaining cavity regions using an SAH process;
wherein forming each such photonic device includes forming a thin insulating layer overlying the plurality of cavity regions and all previously formed photonic devices, removing a portion of the thin insulating layer within a target cavity region, and forming one or more photonic device materials overlying the buffer material within the target cavity region using an SAH process;
forming a third insulating layer overlying the plurality of cavity regions, the active photonic device, the photonic devices, and the thin insulating layers;
and
planarizing the third insulating layer.

18 more elements

A method of fabricating an integrated system having a photonic integrated circuit (PIC) device, the method comprising:

providing a substrate;
forming a first insulating layer overlying the substrate;
forming a multi-layer device stack overlying the second insulating layer, the multi-layer device stack having at least a first device layer overlying the second insulating layer, a first device cladding layer overlying the first device layer, and a second device layer overlying the first cladding layer;
removing one or more portions of the multi-layer device stack to form a plurality of waveguide structures overlying the first insulating layer;
forming a second insulating layer overlying the plurality of waveguide structures and the first insulating layer;
removing one or more portions from the second insulating layer and the first insulating layer to form a plurality of cavity regions, each exposing a surface region of the substrate;
forming a hard mask layer overlying the second insulating layer and the plurality of cavity regions;
removing a plurality of portions from the hard mask layer within a first cavity region of the plurality of cavity regions to form a plurality of trenches, each of which exposes a portion of a surface region of the substrate
removing a plurality of portions from the substrate to form a plurality of v-grooves within the substrate in the first cavity region using the plurality of trenches;
removing the remaining portions of the hard mask layer;
forming a buffer material overlying the exposed surface region of the substrate within each cavity region;
forming an active photonic device within the first cavity region of the plurality of cavity regions, the forming of the active photonic device including forming a plurality of device materials within the first cavity region overlying the surface region of the substrate within the first cavity region using a selective area heteroepitaxy (SAH) process, wherein forming the plurality of device materials comprises
forming an n-type contact material overlying the buffer material within the first cavity region;
forming an n-type lower cladding material overlying the n-type contact material;
forming an active region material overlying the n-type cladding material, wherein the active region material is aligned with at least a portion of the plurality of waveguide structures;
forming a p-type upper cladding material overlying the active region material;
and
forming a p-type contact material overlying the p-type upper cladding material;
forming a photonic device in each of the remaining cavity regions using an SAH process;
wherein forming each such photonic device includes forming a thin insulating layer overlying the plurality of cavity regions and all previously formed photonic devices, removing a portion of the thin insulating layer within a target cavity region, and forming one or more photonic device materials overlying the buffer material within the target cavity region using an SAH process;
forming a third insulating layer overlying the plurality of cavity regions, the active photonic device, the photonic devices, and the thin insulating layers;
and
planarizing the third insulating layer.

20 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/593,471Filed 1 Mar 2024
Granted: 25 Aug 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10F 55/18
Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light…:…
H10F 71/1276
The active layers comprising only Group III-V materials, e.g. GaAs or InP: comprising growth substrates not made of Group III-V materials
H10F 71/139
Manufacture or treatment of devices covered by this subclass: using temporary substrates
H10F 77/413
Optical elements or arrangements: directly associated or integrated with the devices, e.g. back reflectors