Transceiver architecture with low kick-back noise and pad cap

A transceiver, comprising:

• a metal-oxide semiconductor (MOS) device that is electrically connected to an input/output (I/O) pad of the transceiver via a drain terminal of the MOS device;
• and
• a reference voltage kickback reduction circuit electrically connected to a gate terminal of the MOS device such that the reference voltage kickback reduction circuit supplies a reference voltage signal to the gate terminal of the MOS device, the reference voltage kickback reduction circuit is configured to drive the reference voltage signal to dynamically track voltage of the I/O pad when the transceiver is in a receiver mode, the reference voltage kickback reduction circuit includes a first sub-circuit that drives the reference voltage signal when the transceiver is in the receiver mode and the voltage of the I/O pad is maximum, a second sub-circuit drives the reference voltage signal when the transceiver is in the receiver mode and the voltage of the I/O pad is minimum and a third sub-circuit drives the reference voltage signal when the transceiver is in a transmitter mode.

A transceiver comprising:

• a metal-oxide semiconductor (MOS) device that is electrically connected to an input/output (I/O) pad of the transceiver via a drain terminal of the MOS device;
• and
• a reference voltage kickback reduction circuit electrically connected to a gate terminal of the MOS device such that the reference voltage kickback reduction circuit supplies a reference voltage signal to the gate terminal of the MOS device, the reference voltage kickback reduction circuit is configured to drive the reference voltage signal to the voltage of the I/O pad in a receiver mode with a high I/O pad voltage, drive the reference voltage signal to a pre-reference voltage in the receiver mode with a low I/O pad voltage and drive the reference voltage to the pre-reference voltage in a transmitter mode.