Array substrate and display apparatus

An array substrate, comprising a plurality of pixel driving circuits;

• wherein a respective pixel driving circuit of the plurality of pixel driving circuits comprises a driving transistor, a data write transistor, a first capacitor comprising a first capacitor electrode and a second capacitor electrode, and a second capacitor comprising a third capacitor electrode and a fourth capacitor electrode;
• wherein the second capacitor electrode and the third capacitor electrode are coupled to a second electrode of the data write transistor;
• wherein the array substrate comprises a stacked structure of capacitor electrodes;
• wherein the stacked structure comprises:
• the first capacitor electrode;
• an insulating layer on the first capacitor electrode;
• an electrode block comprising the second capacitor electrode and the third capacitor electrode on a side of the insulating layer away from the first capacitor electrode;
• an inter-layer dielectric layer on a side of the electrode block away from the insulating layer;
• and
• the fourth capacitor electrode on a side of the inter-layer dielectric layer away from the electrode block;
• wherein the array substrate further comprises a fourth node portion in a semiconductor material layer;
• wherein the respective pixel driving circuit further comprises a compensating transistor and a second light emitting control transistor;
• wherein the fourth node portion comprises at least a portion of a second electrode of the driving transistor, at least a portion of a first electrode of the compensating transistor, and at least a portion of a first electrode of the second light emitting control transistor;
• and
• an orthographic projection of the fourth node portion on a base substrate at least partially overlaps with an orthographic projection of a respective data line of a plurality of data lines on the base substrate.

An array substrate, comprising a plurality of pixel driving circuits;

• wherein a respective pixel driving circuit of the plurality of pixel driving circuits comprises a driving transistor, a data write transistor, a first capacitor comprising a first capacitor electrode and a second capacitor electrode, and a second capacitor comprising a third capacitor electrode and a fourth capacitor electrode;
• wherein the second capacitor electrode and the third capacitor electrode are coupled to a second electrode of the data write transistor;
• wherein the array substrate comprises a stacked structure of capacitor electrodes;
• wherein the stacked structure comprises:
• the first capacitor electrode;
• an insulating layer on the first capacitor electrode;
• an electrode block comprising the second capacitor electrode and the third capacitor electrode on a side of the insulating layer away from the first capacitor electrode;
• an inter-layer dielectric layer on a side of the electrode block away from the insulating layer;
• and
• the fourth capacitor electrode on a side of the inter-layer dielectric layer away from the electrode block;
• wherein the array substrate further comprises:
• a first data line configured to provide data signals to a first subpixel;
• a second data line configured to provide data signals to a second subpixel;
• a third data line configured to provide data signals to a third subpixel;
• a first anode in the first subpixel;
• a second anode in the second subpixel;
• and
• a third anode in the third subpixel;
• wherein an orthographic projection of a combination of the first anode, the second anode, and the third anode on a base substrate partially overlaps with an orthographic projection of the first data line on the base substrate, partially overlaps with an orthographic projection of the second data line on the base substrate, and is non-overlapping with an orthographic projection of the third data line on the base substrate.