Display device

A display device, comprising:

• a substrate comprising a display area and a peripheral area;
• a pixel comprising a thin-film transistor and a display element, wherein the thin-film transistor is disposed in the display area and comprises a semiconductor layer, a first gate electrode, a second gate electrode, a source electrode, and a drain electrode, and the display element is connected to the thin-film transistor;
• a driving terminal unit disposed in the peripheral area and comprising a controller configured to control transmission of a driving signal to the pixel;
• a terminal disposed in the peripheral area and configured to transmit an inspection signal to the pixel;
• a wire that connects the terminal to the pixel;
• a semiconductor resistor disposed below the terminal;
• an insulating layer disposed between the semiconductor resistor and the terminal;
• a planarization layer comprising a terminal opening, wherein the planarization layer covers a first end of the terminal and a first portion of an upper surface of the terminal extending from the first end, covers a second end of the terminal and a second portion of the upper surface of the terminal extending from the second end, and surrounds the terminal opening;
• a first gate insulating layer having a first portion between the semiconductor resistor and the insulating layer, and having a second portion interposed between the first gate electrode and the second gate electrode;
• and
• a second gate insulating layer having a first portion between the first gate insulating layer and the insulating layer, and having a second portion covering the first and second gate electrodes,
• wherein the semiconductor resistor is in electrical contact with the terminal through a first contact hole defined in the insulating layer,
• wherein the wire is in contact with the semiconductor resistor through a second contact hole defined in the insulating layer,
• wherein a portion of the semiconductor resistor is overlapped by the terminal opening,
• wherein the first portion of the upper surface of the terminal extending from the first end and covered by the planarization layer, the second portion of the upper surface of the terminal extending from the second end and covered by the planarization layer, and a third portion of the upper surface of the terminal that is not covered by the planarization layer and that overlaps one end of the semiconductor resistor are substantially aligned with one another in a cross-sectional view.