Fabrication of reconfigurable architectures using ferroelectrics

A field programmable gate array (FPGA) apparatus, comprising:

• a plurality of digital circuits comprising transistors on a substrate, the digital circuits to implement logic functions;
• a plurality of external interfaces to connect the digital circuits with components external to the FPGA apparatus;
• a plurality of interconnect layers comprising wires and vias surrounded by interlayer dielectric above the substrate, the wires and vias to conductively couple the plurality of digital circuits and the plurality of external interfaces;
• a plurality of programmable switches to configure connections between the plurality of digital circuits and the plurality of external interfaces;
• and
• a ferroelectric material contacting a metal in a conductive path of a gate of one or more of the transistors, wherein the ferroelectric material comprises ferroelectric material in a ferroelectric capacitor, the ferroelectric material comprises a layer of material between a metal gate and a fin body in a fin field effect transistor (FinFET), the ferroelectric material comprises a ferroelectric material in a thin film transistor formed on the interlayer dielectric such that the thin film transistor is to gate power to one or more of the digital circuits, or the ferroelectric material comprises a layer of material between a metal gate and a channel of a planar transistor.

An apparatus, comprising:

• a plurality of logic blocks comprising static random access memory (SRAM) cells comprising transistors on a semiconductor substrate, the logic blocks to implement logic functions;
• a plurality of input/output (I/O) blocks connecting the logic blocks with components external to the apparatus;
• a plurality of interconnect layers comprising wires and vias surrounded by interlayer dielectric above the semiconductor substrate, the wires and vias to conductively couple the plurality of logic blocks and the plurality of I/O blocks;
• a plurality of programmable switches to configure connections between the plurality of logic blocks and the plurality of I/O blocks;
• and
• a ferroelectric material contacting a metal in a conductive path of a gate of one or more of the transistors, wherein the ferroelectric material comprises ferroelectric material in a ferroelectric capacitor, the ferroelectric material comprises a layer of material between a metal gate and a fin body in a fin field effect transistor (FinFET), the ferroelectric material comprises a ferroelectric material in a thin film transistor formed on the interlayer dielectric such that the thin film transistor is to gate power to one or more of the logic blocks, or the ferroelectric material comprises a layer of material between a metal gate and a channel of a planar transistor.