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US 12,720,857 B2Granted
Structure and method to form a stack field effect transistor with different channel oriented gate-all-around devices
AssigneeInternational Business Machines Corporation
InventorsShogo Mochizuki, Gen Tsutsui
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Abstract
A semiconductor device is provided. The semiconductor device includes a stacked field effect transistor (FET) structure. The stacked FET structure includes a bottom FET device and a top FET device. The bottom FET device has a vertically stacked gate-all-around (GAA) nanosheet (NS) structure and a first channel orientation. The top FET device is isolated from the bottom device and has a horizontally stacked structure and a second channel orientation differing from the first channel orientation.
Claims12
A semiconductor device, comprising:
- a stacked field effect transistor (FET) structure comprising bottom and top FET devices and a dielectric layer,
- the bottom FET device having a vertically stacked gate-all-around (GAA) nanosheet (NS) structure and a first channel orientation, the first channel orientation being characterized in that each NS of the bottom FET device is elongate in a channel direction and a horizontal direction,
- the top FET device being isolated from the bottom FET device by the dielectric layer, and
- the top FET device having a horizontally stacked structure and a second channel orientation differing from the first channel orientation, the second channel orientation being characterized in that each NS of the top FET device is elongate in the channel direction and a vertical direction perpendicular to the horizontal direction,
- wherein each NS of the top FET device comprises a vertically oriented semiconductor layer and the top FET device is partially offset from the bottom FET device such that at least one vertically oriented semiconductor layer of the top FET device extends beyond a vertical plane of a sidewall of the bottom FET device.
2 more elements
A semiconductor device, comprising:
- a semiconductor substrate comprising an uppermost surface and a vertical fin extending upwardly from the uppermost surface;
- shallow trench isolation (STI) aside the vertical fin;
- a vertically stacked gate-all-around (GAA) nanosheet (NS) field effect transistor (FET) structure disposed on the vertical fin and comprising nanosheets (NSs) that are elongate in a channel direction and a horizontal direction;
- a dielectric layer disposed on the vertically stacked GAA NS FET structure;
- a horizontally stacked GAA NS FET structure disposed on a portion of the dielectric layer to be isolated from the vertically stacked GAA NS FET structure and comprising NSs that are elongate in the channel direction and a vertical direction;
- and
- high-k metal gate material surrounding the vertically stacked GAA NS FET structure and the horizontally stacked GAA NS FET structure,
- wherein each NS of the horizontally stacked GAA NS FET structure comprises a vertically oriented semiconductor layer and the horizontally stacked GAA NS FET structure is partially offset from the vertically stacked GAA NS FET structure such that at least one vertically oriented semiconductor layer of the horizontally stacked GAA NS FET structure extends beyond a vertical plane of a sidewall of the horizontally stacked GAA NS FET structure.
5 more elements
Dependencies are inferred from the claim text.