Capacitor structure embedded within source or drain region

An integrated circuit comprising:

• a semiconductor region over a substrate and extending in a first direction from a first source or drain region to a second source or drain region;
• a gate structure extending in a second direction over the semiconductor region;
• a first conductive layer contacting a first sidewall portion of the first source or drain region;
• a ferroelectric layer on the first conductive layer and contacting a second sidewall portion of the source or drain region;
• a second conductive layer on the ferroelectric layer;
• and
• a conductive contact on the second conductive layer.

An integrated circuit comprising:

• a semiconductor region over a substrate and extending in a first direction from a first source or drain region to a second source or drain region;
• a gate structure extending in a second direction over the semiconductor region;
• a dielectric spacer structure between the gate structure and the source or drain region along the first direction and directly contacting both the gate structure and the source or drain region;
• a conductive layer directly on a top surface of the first source or drain region;
• a ferroelectric layer on the conductive layer;
• and
• a conductive contact on the ferroelectric layer, wherein a top surface of the conductive contact is not above a top surface of the dielectric spacer structure.