Semiconductor device with recessed gate and method for fabricating the same

A method for fabricating a semiconductor device, comprising:

• providing a substrate comprising a first peripheral region and a second peripheral region;
• forming a mandrel layer on the first peripheral region;
• conformally forming a layer of spacer material on the substrate and covering the mandrel layer;
• performing a spacer etching process to turn the layer of spacer material into a plurality of sacrificial spacers on sides of the mandrel layer;
• forming an under layer on the substrate and covering the mandrel layer and the plurality of sacrificial spacers;
• recessing the under layer to expose the mandrel layer and the plurality of sacrificial spacers;
• selectively removing the plurality of sacrificial spacers to expose the first peripheral region;
• forming a plurality of gate recesses in the first peripheral region;
• and
• forming a plurality of recessed gates on the plurality of gate recesses;
• wherein the layer of spacer material is formed by atomic layer deposition;
• wherein forming the plurality of recessed gates on the plurality of gate recesses comprises:
• conformally forming a layer of gate dielectric material on both the substrate and within the plurality of gate recesses;
• forming a layer of first conductive material on the layer of gate dielectric material, resulting in the formation of a plurality of first valleys within the plurality of gate recesses, respectively and correspondingly;
• conformally forming a layer of second conductive material on the layer of first conductive material, resulting in the formation of a plurality of second valleys within the plurality of gate recesses, respectively and correspondingly;
• forming a layer of top insulating material on the layer of second conductive material, completely filling the plurality of second valleys;
• and
• patterning the layer of gate dielectric material, the layer of first conductive material, the layer of second conductive material, and the layer of top insulating material to form, respectively and correspondingly, a plurality of recessed gate dielectric layers, a plurality of recessed gate bottom conductive layers, a plurality of recessed gate top conductive layers, and a plurality of recessed gate capping layers within the plurality of gate recesses;
• wherein the plurality of recessed gate dielectric layers, the plurality of recessed gate bottom conductive layers, the plurality of recessed gate top conductive layers, and the plurality of recessed gate capping layers together configure the plurality of recessed gates.