Integrated circuit structure and method for forming the same
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
InventorsShih-Yen Lin, Che-Jia Chang
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Abstract
A method includes performing a first deposition process to form a first graphene layer over a substrate, the first deposition process being performed under a first temperature and a first pressure; performing a second deposition process to form a second graphene layer over the first graphene layer, the second deposition process being performed under a second temperature and a second pressure, in which the first temperature is higher than the second temperature, and the first pressure is lower than the second pressure; forming a gate structure over the second graphene layer; and forming source/drain contacts on opposite sides of the gate structure and electrically connected to the first and second graphene layers.
Claims20
A method, comprising:
- performing a first deposition process to form a first graphene layer over a substrate, the first deposition process being performed under a first temperature and a first pressure;
- performing a second deposition process to form a second graphene layer over the first graphene layer, the second deposition process being performed under a second temperature and a second pressure, wherein the first temperature is higher than the second temperature, and the first pressure is lower than the second pressure, wherein the first deposition process and the second deposition process both are performed using precursors comprising Ar, H2, and C2H6, and wherein a flow rate of H2 in the first deposition process is lower than a flow rate of H2 in the second deposition process;
- forming a gate structure over the second graphene layer;
- and
- forming source/drain contacts on opposite sides of the gate structure and electrically connected to the first and second graphene layers.
A method, comprising:
- forming a transistor over a substrate;
- forming a dielectric layer over the transistor;
- patterning the dielectric layer to form an opening;
- depositing a first 2-D material layer over the dielectric layer and lining the opening;
- depositing a second 2-D material layer lining the first 2-D material layer, wherein the second 2-D material layer is made of a different material than the first 2-D material layer, wherein the second 2-D material layer is made of a metal-containing material, wherein a bottom surface of the second 2-D material layer is higher than a bottom surface of the first 2-D material layer, and wherein the first 2-D material layer interfaces with a top surface of a channel layer of the transistor and the bottom surface of the second 2-D material layer;
- depositing a metal layer over the second 2-D material layer;
- and
- performing a planarization process to the first 2-D material layer, the second 2-D material layer, and the metal layer to form an interconnect structure electrically connected to the transistor, wherein the interconnect structure comprises remaining portions of the first 2-D material layer, the second 2-D material layer, and the metal layer.
A method, comprising:
- forming a transistor over a substrate, wherein the transistor comprises a 2-D material channel layer;
- forming a dielectric layer over the transistor;
- and
- forming a contact in the dielectric layer and electrically connected to the transistor, wherein the contact comprises:
- a first metal-free 2-D material layer interfacing with the 2-D material channel layer of the transistor;
- a first metal-containing 2-D material layer;
- and
- a first metal layer over the first metal-containing 2-D material layer, wherein the first metal layer has a dual damascene structure comprising a via portion and a metal line portion over the via portion, the metal line portion being wider than the via portion, and the first metal-containing 2-D material layer has a horizontal portion interfacing with a bottom surface of the metal line portion.
Dependencies are inferred from the claim text.