Silicon carbide semiconductor device

A silicon carbide semiconductor device, comprising:

• a semiconductor substrate containing silicon carbide and having a first main surface and a second main surface opposite to each other;
• a first semiconductor region of a first conductivity type, provided in the semiconductor substrate;
• a second semiconductor region of a second conductivity type, provided between the first main surface of the semiconductor substrate and the first semiconductor region;
• a third semiconductor region of the first conductivity type, selectively provided between the first main surface and the second semiconductor region;
• a trench penetrating through the third semiconductor region and the second semiconductor region in a depth direction of the device;
• a gate electrode provided in the trench via a gate insulating film;
• a plurality of high-concentration regions of the second conductivity type, selectively provided between the second semiconductor region and the first semiconductor region, at positions closer to the second main surface than is a bottom of the trench, each of the plurality of high-concentration regions having an impurity concentration higher than an impurity concentration of the second semiconductor region, a bottom of each of the plurality of high-concentration regions being at a position closer to the second main surface than is a bottom of the trench;
• a junction field effect transistor (JFET) region of the first conductivity type, selectively provided between the second semiconductor region and the first semiconductor region, the JFET region being in contact with the first semiconductor region, the second semiconductor region, and the plurality of high-concentration regions, the JFET region having an impurity concentration higher than the impurity concentration of the first semiconductor region, a bottom of the JFET region being at a position closer to the second main surface than is the bottom of the trench;
• a first electrode electrically connected to the third semiconductor region, the second semiconductor region, and the plurality of high-concentration regions;
• and
• a second electrode provided at the second main surface, wherein
• the plurality of high-concentration regions include:
• a first high-concentration region provided apart from the second semiconductor region and facing the bottom of the trench in the depth direction, and
• a second high-concentration region in contact with the second semiconductor region and provided apart from the trench and the first high-concentration region,
• the first high-concentration region extends closer to the second high-concentration region than is a sidewall of the trench in a direction parallel to the first main surface, by an overhang length,
• the JFET region includes:
• a first JFET region provided between and in contact with the first high-concentration region and the second high-concentration region that are adjacent to each other and apart from the sidewall of the trench, and
• a second JFET region provided between and in contact with the second semiconductor region and the first JFET region, the second JFET region extending from the first JFET region between the second semiconductor region and the first high-concentration region and reaching the sidewall of the trench, and
• a thickness in the depth direction of the second JFET region is not more than the overhang length of the first high-concentration region.