Device and method for inhibiting a substrate current in an IC semiconductor substrate

A device for monitoring a potential of a monitoring circuit node of a CMOS circuit, comprising the monitor circuit node,

• the monitoring circuit node lying in a region doped with charge carriers of a second conductivity type, or being electrically connected to one or more such regions,
• the one or more such doped regions being formed in a semiconductor substrate doped with charge carriers of a first conductivity type opposite to the second conductivity type,
• the semiconductor substrate having a plurality of doped regions, which each form electronic components or in which electronic components are formed, and being acted upon by a substrate potential,
• the CMOS circuit having a reference potential and an output driver stage for actuating an activating element of a passive vehicle safety system,
• wherein the output driver stage has two external terminal contacts which are to be led out or which are led out and a high-side output transistor, as well as a low-side output transistor, each of which is connected to a different one of the two external terminal contacts, wherein each of the external contacts is configured to connect to the actuating or activating element, and
• wherein the monitoring circuit node includes at least one of the two external contacts configured to be connected to the actuating or activating element,
• a parasitic bipolar lateral structure being formed, between the doped region having the monitoring circuit node and at least one doped region adjacent to this doped region or between at least one of the doped regions, to which the monitoring circuit node is electrically connected, and a doped region adjacent to this doped region or a doped region adjacent to one of these doped regions,
• the device further comprising:
• a comparator circuit for comparing the potential of the monitoring circuit node with a reference potential which is equal to or lower than the reference potential or equal to both the substrate potential and the reference potential or lower than both the substrate potential and the reference potential,
• wherein the comparator circuit directly or indirectly generates a switching signal for switching an electronic switch to conduction, said electronic switch being able to be arranged between the monitoring circuit node and a leakage circuit node for discharging current, when a detected potential value is lower than or equal to the reference potential, and thus the generation of a substrate current in the bipolar later in the semiconductor substrate is suppressed, and
• wherein the electronic switch is the low-side output transistor of the output driver stage and the monitoring circuit node is the external terminal contact of the output driver stage which is connected to the low-side output transistor.

A method for preventing a laterally directed substrate current from being generated in a semiconductor substrate doped with charge carriers of a first conductivity type in which a CMOS circuit is integrated and which has

• a plurality of regions doped with charge carriers of a second conductivity type that is opposite to a first conductivity type, which each form electronic components or in which electronic components are each formed,
• a monitoring circuit node, which lies in one of the doped regions or is electrically connected to one or more of the doped regions and is to be monitored with regard to its potential,
• the semiconductor substrate having a substrate potential applied thereto,
• the CMOS circuit having a reference potential and an output driver stage for actuating an activating element of a passive vehicle safety system,
• wherein the output driver stage has two external terminal contacts which are to be led out or which are led out and a high-side output transistor, as well as a low-side output transistor, each of which is connected to a different one of the two external terminal contacts, wherein each of the external contacts is configured to connect to the actuating or activating element, and
• wherein the monitoring circuit node includes at least one of the two external contacts configured to be connected to the actuating or activating element,
• a parasitic bipolar lateral structure being formed, between the doped region having the monitoring circuit node and at least one doped region adjacent to this doped region or between at least one of the doped regions, to which the monitoring circuit node is electrically connected, and a doped region adjacent to this doped region or a doped region adjacent to one of these doped regions,
• comprising, during operation of the CMOS circuit:
• detecting a potential value representing the potential at the monitoring circuit node,
• comparing the detected potential value with a reference potential equal to or lower than the substrate potential, or equal to or lower than the reference potential, or equal to both the substrate potential and the reference potential, or lower than both the substrate potential and the reference potential, and
• connecting the monitoring circuit node to a leakage circuit node serving to discharge current when the potential value is equal to or lower than the reference value, whereby the generation of a substrate current in the bipolar later in the semiconductor substrate, is suppressed,
• detecting the potential of the external terminal contact of the output driver stage, which is connected to the low-side output transistor, and
• connecting this external terminal contact to the leakage circuit node by switching to conduction of the low-side output transistor of the output driver stage which is connected to the leakage circuit node.

A device for use in an integrated CMOS circuit, which is integrated in a semiconductor substrate doped with charge carriers of a first conductivity type, in particular in a p-doped semiconductor substrate, the semiconductor substrate having

• a plurality of regions doped with charge carriers of a second conductivity type that is opposite to the first conductivity type, in particular a plurality of n-doped N-regions, which each form electronic components or in which electronic components are each formed,
• a monitoring circuit node, which lies in one of the doped regions or is electrically connected to one or more of the doped regions and is to be monitored with regard to its potential,
• the semiconductor substrate having a substrate potential applied thereto,
• the CMOS circuit having a reference potential and
• a parasitic bipolar lateral structure being formed, in particular a parasitic bipolar NPN lateral structure, between the doped region having the monitoring circuit node and at least one doped region adjacent to this doped region or between at least one of the doped regions, to which the monitoring circuit node is electrically connected, and a doped region adjacent to this doped region or a doped region adjacent to one of these doped regions,
• comprising:
• a current source, an ohmic resistor and a first transistor, which are connected in series between a supply potential and the reference potential,
• wherein the first transistor has a conduction path arranged between the ohmic resistor and the reference potential and a control electrode,
• wherein the current source feeds a current into a first circuit node of the series circuit composed of the resistor and the first transistor,
• wherein the first circuit node and the control electrode of the first transistor are electrically connected to one another, and
• a second transistor having a conduction path and a control electrode,
• wherein the conduction path of the second transistor is connected between the monitoring circuit node and a leakage circuit node,
• a second circuit node of the series circuit which is arranged between the ohmic resistor and the first transistor and is electrically connected to the control electrode of the second transistor,
• wherein the second transistor conducts when the potential of the monitoring circuit node undershoots a predetermined reference value, which is defined by, among other things, the resistor and/or threshold voltages of the two transistors or a difference in the threshold voltages of the two transistors and/or sizes of the control electrodes of the two transistors or the difference in the sizes of the control electrodes of the two transistors.