Partial gate cut structures in an integrated circuit

An electronic device, comprising:

• a chip package comprising one or more dies, at least one of the one or more dies comprising a first semiconductor device having a first semiconductor region extending in a first direction between a first source region and a first drain region;
• a second semiconductor device having a second semiconductor region extending in the first direction between a second source region and a second drain region, the second semiconductor device spaced from the first semiconductor device in a second direction different from the first direction;
• a gate layer around each of the first semiconductor region and the second semiconductor region;
• a gate dielectric layer around the first semiconductor region and the second semiconductor region, such that the gate dielectric layer is between the first semiconductor region and the gate layer and is between the second semiconductor region and the gate layer, wherein the gate dielectric layer comprises a high-k dielectric layer;
• and
• a dielectric pillar between the first semiconductor device and the second semiconductor device, such that the gate layer extends beneath a bottom surface of the dielectric pillar and directly contacts the entire bottom surface of the dielectric pillar, wherein the gate dielectric layer does not extend along sidewalls of the dielectric pillar.

An integrated circuit comprising:

• a gate layer extending in a first direction over one or more semiconductor regions of one or more corresponding semiconductor devices;
• a gate dielectric layer around the one or more semiconductor regions, such that the gate dielectric layer is between the one or more semiconductor regions and the gate layer,
• wherein the gate dielectric layer comprises a high-k dielectric layer;
• a first dielectric pillar adjacent to at least one of the one or more semiconductor devices and having a height extending along at least an entire height of the gate layer;
• and
• a second dielectric pillar adjacent to the at least one of the one or more semiconductor devices, wherein the gate layer extends beneath a bottom surface of the second dielectric pillar and directly contacts the entire bottom surface of the second dielectric pillar, and wherein the gate dielectric layer extends along a sidewall of the first dielectric pillar and does not extend along sidewalls of the second dielectric pillar.