Bonding and isolation techniques for stacked transistor structures

A stacked device structure comprising:

• a gate stack that includes a first gate disposed over a second gate, wherein the first gate engages a first channel layer and the second gate engages a second channel layer;
• a first source/drain stack and a second source/drain stack, wherein the gate stack is disposed between the first source/drain stack and the second source/drain stack, the first source/drain stack includes a first source/drain disposed over a second source/drain, the second source/drain stack includes a third source/drain disposed over a fourth source/drain, the first channel layer is disposed between the first source/drain and the third source/drain, and the second channel layer is disposed between the second source/drain and the fourth source/drain;
• wherein the gate stack further includes a gate isolation structure disposed between the first gate and the second gate, wherein the gate isolation structure includes a first insulation layer having a first composition and a second insulation layer having a second composition, wherein the second composition is different than the first composition;
• and
• wherein the first source/drain stack further includes a first source/drain isolation structure disposed between the first source/drain and the second source/drain and the second source/drain stack further includes a second source/drain isolation structure disposed between the third source/drain and the fourth source/drain, and the gate isolation structure is disposed between the first source/drain isolation structure and the second source/drain isolation structure.

A stacked device structure comprising:

• a first transistor having a first semiconductor layer and a first gate, wherein the first gate is disposed over a top and a bottom of the first semiconductor layer;
• a second transistor having a second semiconductor layer and a second gate, wherein the second gate is disposed over a top and a bottom of the second semiconductor layer, wherein the first gate is disposed over the second gate;
• and
• a gate isolation structure disposed between the first gate and the second gate, wherein the gate isolation structure includes a nitride portion and an oxide portion.