Lightly-doped channel extensions
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Jen Lai, Wei-Yuan Lu, Chih-Hao Yu, Chia-Pin Lin
Life of this patent
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Abstract
A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.
Claims20
A semiconductor structure, comprising:
- an active region comprising a channel region and a source/drain region adjacent the channel region;
- a plurality of nanostructures disposed over the channel region;
- a plurality of channel extension features, at least one of the plurality of channel extension features interfacing an end surface of one of the plurality of nanostructures;
- a bottom epitaxial layer over the source/drain region;
- and
- a source/drain feature disposed over the bottom epitaxial layer and in direct contact with the plurality of channel extension features,
- wherein a composition of the plurality of channel extension features and a composition of the bottom epitaxial layer are the same,
- wherein a composition of the plurality of nanostructures is different from the composition of the plurality of channel extension features.
A semiconductor structure, comprising:
- an active region comprising a channel region disposed between a first source/drain region and a second source/drain region;
- a first source/drain feature disposed over the first source/drain region;
- a second source/drain feature disposed over the second source/drain region;
- a plurality of channel members disposed over the channel region and extending between the first source/drain feature and the second source/drain feature along a direction;
- a first plurality of channel extension features disposed between the first source/drain feature and the plurality of channel members along the direction;
- and
- a bottom epitaxial feature disposed between the first source/drain region and the first source/drain feature as well as between the second source/drain region and the second source/drain feature,
- wherein the bottom epitaxial feature interfaces a surface of the first source/drain region.
A method, comprising:
- receiving a workpiece comprising:
- a substrate, and
- a fin-shaped structure over the substrate and comprising a channel region and a source/drain region adjacent the channel region, wherein the fin-shaped structure comprises a plurality of channel layers interleaved by a plurality of sacrificial layers;
- forming a dummy gate stack over the channel region;
- recessing the source/drain region to form a source/drain trench that exposes sidewalls of the plurality of channel layers and the plurality of sacrificial layers;
- selectively and partially recessing the plurality of sacrificial layers to form a plurality of inner spacer recesses;
- forming a plurality of inner spacer features in the plurality of inner spacer recesses;
- after the forming of the plurality of inner spacer features, selectively trimming the plurality of channel layers to form end surfaces;
- selectively depositing a semiconductor layer on the end surfaces to form channel extension features in contact with the end surfaces;
- after the selectively depositing, forming a source/drain feature in the source/drain trench to be in contact with the channel extension features;
- and
- after the forming of the source/drain feature, replacing the dummy gate stack with a gate structure,
- wherein the recessing also exposes a portion of the substrate,
- wherein the selectively depositing comprises depositing a bottom epitaxial layer over the exposed portion of the substrate.
Dependencies are inferred from the claim text.