Gate dielectric layers for stacked multi-gate device

A method, comprising:

• receiving a workpiece comprising:
• a substrate,
• a first gate structure wrapping around each of first bottom channel members over a first region of the substrate,
• a second gate structure wrapping around each of second bottom channel members over a second region of the substrate, and
• a third gate structure wrapping around each of third bottom channel members over a third region of the substrate;
• forming first top channel members over the first gate structure, second top channel members over the second gate structure, and third top channel members over the third gate structure;
• depositing a first gate dielectric layer to wrap around each of the first top channel members, each of the second top channel members, and each of the third top channel members;
• selectively depositing a first dipole layer to wrap around each of the third top channel members;
• performing a first anneal process to drive a first dopant in the first dipole layer into the first gate dielectric layer around the third top channel members;
• removing the first dipole layer;
• and
• after the removing, depositing a second gate dielectric layer to wrap around each of the first top channel members, each of the second top channel members, and each of the third top channel members.

A semiconductor structure, comprising:

• a substrate comprising a first region, a second region, and a third region;
• first channel members over the first region;
• second channel members over the second region;
• third channel members over the third region;
• a first gate structure wrapping around each of the first channel members and comprising:
• a first gate dielectric layer in contact with each of the first channel members,
• a second gate dielectric layer over the first gate dielectric layer,
• a third gate dielectric layer over the second gate dielectric layer, and
• a first gate electrode;
• a second gate structure wrapping around each of the second channel members and comprising:
• the first gate dielectric layer in contact with each of the second channel members,
• a fourth gate dielectric layer over the first gate dielectric layer,
• the third gate dielectric layer over the fourth gate dielectric layer, and
• a second gate electrode;
• and
• a third gate structure wrapping around each of the third channel members and comprising:
• a fifth gate dielectric layer in contact with each of the third channel members,
• the fourth gate dielectric layer over the fifth gate dielectric layer,
• the third gate dielectric layer over the fourth gate dielectric layer, and
• a third gate electrode,
• wherein a composition of the first gate dielectric layer is different from a composition of the fourth gate dielectric layer,
• wherein a composition of the third gate dielectric layer is different from the composition of the fourth gate dielectric layer,
• wherein the first gate dielectric layer and the fourth gate dielectric layer comprise hafnium oxide, hafnium zirconium oxide, or zirconium oxide.