Fabrication of gate-all-around integrated circuit structures having pre-spacer-deposition wide cut gates

An integrated circuit structure, comprising:

• a first fin;
• a second fin;
• a first gate stack over the first fin, the first gate stack including a first gate dielectric and a first gate electrode;
• a second gate stack over the second fin, the second gate stack including a second gate dielectric and a second gate electrode, an end of the second gate stack spaced apart from an end of the first gate stack by a gap;
• a first dielectric gate spacer along an end of the first gate stack in the gap, wherein the first gate dielectric is along the first dielectric gate spacer and is separate and distinct from the first dielectric gate spacer;
• a second dielectric gate spacer along an end of the second gate stack in the gap, wherein the second gate dielectric is along the second dielectric gate spacer and is separate and distinct from the second dielectric gate spacer;
• and
• a dielectric material in the gap and laterally between and in contact with the first dielectric gate spacer and the second dielectric gate spacer.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first vertical arrangement of horizontal nanowires;
• a second vertical arrangement of horizontal nanowires;
• a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack including a first gate dielectric and a first gate electrode;
• a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack including a second gate dielectric and a second gate electrode, an end of the second gate stack spaced apart from an end of the first gate stack by a gap;
• a first dielectric gate spacer along an end of the first gate stack in the gap, wherein the first gate dielectric is along the first dielectric gate spacer and is separate and distinct from the first dielectric gate spacer;
• a second dielectric gate spacer along an end of the second gate stack in the gap, wherein the second gate dielectric is along the second dielectric gate spacer and is separate and distinct from the second dielectric gate spacer;
• and
• a dielectric material in the gap and laterally between and in contact with the first dielectric gate spacer and the second dielectric gate spacer.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first fin;
• a second fin;
• a first gate stack over the first fin, the first gate stack including a first gate dielectric and a first gate electrode;
• a second gate stack over the second fin, the second gate stack including a second gate dielectric and a second gate electrode, an end of the second gate stack spaced apart from an end of the first gate stack by a gap;
• a first dielectric gate spacer along an end of the first gate stack in the gap, wherein the first gate dielectric is along the first dielectric gate spacer and is separate and distinct from the first dielectric gate spacer;
• a second dielectric gate spacer along an end of the second gate stack in the gap, wherein the second gate dielectric is along the second dielectric gate spacer and is separate and distinct from the second dielectric gate spacer;
• and
• a dielectric material in the gap and laterally between and in contact with the first dielectric gate spacer and the second dielectric gate spacer.