Semiconductor device

A semiconductor device comprising:

• a semiconductor substrate having an upper surface;
• a substrate region of a first conductivity type formed in the semiconductor substrate;
• a first MISFET formed on the upper surface of the semiconductor substrate;
• a first source region of a second conductivity type opposite the first conductivity type and a first drain region of the second conductivity type, the first source region and the first drain region being formed in the substrate region and spaced apart from each other, the first source region and the first drain region being of the first MISFET;
• a first gate electrode of the first MISFET formed on the semiconductor substrate between the first source region and the first drain region via a first gate dielectric film;
• a first semiconductor region of the first conductivity type formed in the substrate region so as to partially overlap with the first gate electrode in plan view, the first semiconductor region having an impurity concentration higher than an impurity concentration of the substrate region;
• a second semiconductor region of the first conductivity type formed in the substrate region so as not to overlap with the first gate electrode in plan view and so as to be adjacent to the first source region, the second semiconductor region having an impurity concentration higher than the impurity concentration of the first semiconductor region;
• a third semiconductor region of the second conductivity type formed in the substrate region so as to partially overlap with the first gate electrode in plan view and electrically connected to the first drain region, the third semiconductor region having an impurity concentration lower than an impurity concentration of the first drain region;
• and
• an STI region formed at the upper surface of the semiconductor substrate, the STI region being formed in the third semiconductor region and disposed between the first drain region and the first source region,
• wherein the first gate electrode extends in a first direction along the upper surface of the semiconductor substrate,
• wherein the first semiconductor region extends in the first direction so as to cover a bottom surface of the first source region and a bottom surface of the second semiconductor region,
• wherein the semiconductor substrate includes a first region and a second region alternately disposed in the first direction,
• wherein a width of the first semiconductor region, between the first source region and an end portion facing the third semiconductor region of the first semiconductor region, overlapping with the first gate electrode in a second direction in the second region is smaller than a width of the first semiconductor region, between the first source region and the end portion facing the third semiconductor region of the first semiconductor region, overlapping with the first gate electrode in the second direction in the first region,
• wherein the first semiconductor region and the third semiconductor region are spaced apart from each other in the second direction, and
• wherein the second direction is orthogonal to the first direction and along the upper surface of the semiconductor substrate.