High electron mobility transistors with low specific on-resistance

A transistor, comprising:

• a plurality of electrodes forming a source, a gate, and a drain of the transistor;
• and
• a layered semiconductor structure electrically connected to the plurality of electrodes, the layered semiconductor structure comprising:
• a channel layer having a shape formed by a series of fins;
• and
• a barrier layer on the channel layer such that the barrier layer coats the fins of the channel layer to define a shape formed by a series of wells, wherein the series of wells of the barrier layer are interdigitated with the series of fins of the channel layer, wherein the barrier layer comprises a polar piezoelectric material having a first lattice constant, wherein the channel layer comprises a polar material having a second lattice constant, and wherein the second lattice constant is greater than the first lattice constant;
• wherein a shape of each of the source and the drain has a set of electrode fins on a side that forms electrical contact with the barrier layer, and wherein the set of electrode fins of the source and the drain are coupled with the series of wells of the barrier layer and interdigitated with the series of fins of the channel layer.