Semiconductor device and method of manufacturing same

A semiconductor device comprising:

• a substrate including an active pattern;
• a channel pattern on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns;
• a source/drain pattern connected to the plurality of semiconductor patterns;
• a gate electrode on the plurality of semiconductor patterns, wherein the gate electrode includes a portion interposed between adjacent ones of the plurality of semiconductor patterns;
• and
• an inner spacer comprising a first side surface facing the portion of the gate electrode and comprising a second side surface opposite the first side surface, wherein the second side surface includes a first crystal plane contacting a second crystal plane of the source/drain pattern,
• wherein the inner spacer includes crystalline metal oxide and is expressed by a formula (MO), wherein (O) is an oxygen atom, and (M) is a metal atom selected from a group consisting of Mg, Be, and Ga,
• wherein the metal atom (M) of the first crystal plane of the inner spacer and a silicon atom of the second crystal plane of the source/drain pattern are covalently bonded at an interface between the first crystal plane of the inner spacer and the second crystal plane of the source/drain pattern,
• wherein the first crystal plane is configured to lattice match the second crystal plane at the interface between the first crystal plane and the second crystal plane, and
• wherein an atomic ratio of the oxygen atom (O) to the metal atom (M) is 1:1.

A semiconductor device comprising:

• a substrate including an active region;
• a device isolation layer defining an active pattern on the active region;
• a channel pattern and a source/drain pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns;
• a gate electrode on the plurality of semiconductor patterns, the gate electrode including a portion interposed between adjacent semiconductor patterns among the plurality of semiconductor patterns;
• a gate insulating layer between the adjacent semiconductor patterns and the portion of the gate electrode;
• an inner spacer between the gate insulating layer and the source/drain pattern;
• a gate spacer on a sidewall of the gate electrode;
• a gate capping pattern on an upper surface of the gate electrode;
• an interlayer insulating layer on the gate capping pattern;
• an active contact electrically connected to the source/drain pattern through the interlayer insulating layer;
• a metal-semiconductor compound layer interposed between the active contact and the source/drain pattern;
• a gate contact passing through the interlayer insulating layer and the gate capping pattern to be electrically connected to the gate electrode;
• a first metal layer on the interlayer insulating layer, the first metal layer including a power wiring, and first wirings electrically connected to the active contact and the gate contact, respectively;
• and
• a second metal layer on the first metal layer,
• wherein the second metal layer includes second wirings electrically connected to the first metal layer,
• wherein the inner spacer includes crystalline metal oxide of a face-centered cubic structure (FCC),
• wherein the inner spacer comprises a first side surface facing the gate insulating layer and comprises a second side surface opposite the first side surface, wherein the second side surface contacts the source/drain pattern,
• wherein the inner spacer includes crystalline metal oxide and is expressed by a formula (MO), wherein (O) is an oxygen atom, and (M) is a metal atom selected from a group consisting of Mg, Be, and Ga,
• wherein the second side surface comprises a first crystal plane configured to lattice match a second crystal plane of the source/drain pattern at an interface between the first crystal plane and the second crystal plane, and
• wherein an atomic ratio of the oxygen atom (O) to the metal atom (M) is 1:1.