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US 12,720,766 B2Granted
Multi-level memristor elements
AssigneeCirrus Logic, Inc.
InventorsJohn P. Lesso, James T. Deas
Life of this patent
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Abstract
There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.
Claims18
A multi-level programmable resistance memory cell comprising:
- first and second resistance nodes;
- and
- a programmable resistance network connected between the first and second resistance nodes, wherein the programmable resistance network comprises a first plurality of charge-trapping-transistors;
- wherein the multi-level programmable resistance memory cell is operable in:
- a programming mode to selectively programme each of the first plurality of charge-trapping-transistors to a selected on-resistance state by programming an amount of charge trapped in the charge-trapping-transistor;
- and
- an output mode in which each of the first plurality of charge-trapping-transistors is driven with a respective gate-source voltage;
- wherein the multi-level programmable resistance memory cell is configured such that a cell resistance between the first and second resistance nodes in the output mode can be selectively varied between at least three different resistance values by programming of the first plurality of charge-trapping-transistors in the programming mode;
- wherein each of said first plurality of charge-trapping-transistors is arranged in a respective one of a plurality of parallel branches of the resistance network;
- and
- wherein one or more of said parallel branches of the resistance network comprise a fixed resistor in series with the charge-trapping-transistor, where the resistance value of the fixed resistor is different in different parallel branches.
8 more elements
A multi-level programmable resistance memory cell comprising:
- first and second resistance nodes;
- and
- a programmable resistance network connected between the first and second resistance nodes, wherein the programmable resistance network comprises a first plurality of charge-trapping-transistors;
- wherein the multi-level programmable resistance memory cell is operable in:
- a programming mode to selectively programme each of the first plurality of charge-trapping-transistors to a selected on-resistance state by programming an amount of charge trapped in the charge-trapping-transistor;
- and
- an output mode in which each of the first plurality of charge-trapping-transistors is driven with a respective gate-source voltage;
- wherein the multi-level programmable resistance memory cell is configured such that a cell resistance between the first and second resistance nodes in the output mode can be selectively varied between at least three different resistance values by programming of the first plurality of charge-trapping-transistors in the programming mode;
- wherein each of said first plurality of charge-trapping-transistors is arranged in a respective one of a plurality of parallel branches of the resistance network;
- and
- wherein one or more of said parallel branches of the resistance network comprises an active resistance element configured to provide an on-resistance value in series with the charge-trapping-transistor, wherein the active resistance element comprises a transistor.
8 more elements
A multi-level programmable resistance memory cell
- comprising:
- first and second resistance nodes;
- and
- a programmable resistance network connected between the first and second resistance nodes, wherein the programmable resistance network comprises a first plurality of charge-trapping-transistors;
- wherein the multi-level programmable resistance memory cell is operable in:
- a programming mode to selectively programme each of the first plurality of charge-trapping-transistors to a selected on-resistance state by programming an amount of charge trapped in the charge-trapping-transistor;
- and
- an output mode in which each of the first plurality of charge-trapping-transistors is driven with a respective gate-source voltage;
- wherein the multi-level programmable resistance memory cell is configured such that a cell resistance between the first and second resistance nodes in the output mode can be selectively varied between at least three different resistance values by programming of the first plurality of charge-trapping-transistors in the programming mode;
- wherein each of said first plurality of charge-trapping-transistors is arranged in a respective one of a plurality of parallel branches of the resistance network;
- and
- wherein said resistance network comprises a plurality of series connected fixed resistors and wherein each of said first plurality of charge-trapping-transistors is connected in parallel with a different number of said series connected fixed resistors.
9 more elements
A multi-level programmable resistance memory cell comprising:
- first and second resistance nodes;
- and
- a programmable resistance network connected between the first and second resistance nodes, wherein the programmable resistance network comprises a first plurality of charge-trapping-transistors;
- wherein the multi-level programmable resistance memory cell is operable in:
- a programming mode to selectively programme each of the first plurality of charge-trapping-transistors to a selected on-resistance state by programming an amount of charge trapped in the charge-trapping-transistor;
- and
- an output mode in which each of the first plurality of charge-trapping-transistors is driven with a respective gate-source voltage;
- wherein the multi-level programmable resistance memory cell is configured such that a cell resistance between the first and second resistance nodes in the output mode can be selectively varied between at least three different resistance values by programming of the first plurality of charge-trapping-transistors in the programming mode;
- and
- configured to programme said first plurality of charge-trapping-transistors in a sequential process;
- and
- configured such that, in the programming mode, a value for on-resistance of the multi-level programmable resistance memory cell is determined after programming of each charge-trapping-transistor in said sequential process and wherein the programming of a subsequent charge-trapping-transistor in said sequential process is controlled to compensate for any inaccuracy in said determined value for on-resistance of the multi-level programmable resistance memory cell.
9 more elements
Dependencies are inferred from the claim text.