Method of fabricating a memory device by wafer bonding

A method of fabricating a device array, the method comprising:

• depositing a multi-layer stack above a first substrate, the multi-layer stack comprising a plurality of electrode layers and a first dielectric layer comprising a non-linear polar material having a form ABB′O3, AA′B′O3, or ABO3;
• forming a second dielectric layer on the multi-layer stack;
• annealing the multi-layer stack;
• forming a first transistor and a second transistor above a second substrate;
• forming a third dielectric layer above the first transistor and the second transistor;
• bonding the second dielectric layer with the third dielectric layer;
• etching the multi-layer stack to form a first capacitor, and a second capacitor, wherein the first capacitor and the second capacitor comprise a shared plate electrode;
• and
• forming an electrode structure through at least a portion of the shared plate electrode, the electrode structure coupled with a bridge structure, wherein the bridge structure is coupled with the first transistor and the second transistor.