Three dimensional flash memory with bulk erasing

A 3D flash memory employing a cell on peripheral circuit (COP) structure, comprising:

• a substrate comprising at least one transistor of a peripheral circuit formed based on the COP structure;
• at least one memory cell string extending in a first direction from an upper portion of the at least one transistor;
• and
• a connection part comprising an epitaxial structure connected to the at least one memory cell string, the epitaxial structure being in direct contact with the substrate.

A 3D flash memory for integration, comprising:

• a first memory cell array comprising:
• at least one first memory cell string extending in a vertical direction;
• and
• first wordlines connected to the at least one first memory cell string and extending in a horizontal direction perpendicularly to the at least one first memory cell string, wherein the first wordlines are stacked, extend with mutually different lengths, and respectively comprise a step part and a plan part;
• a second memory cell array comprising:
• at least one second memory cell string extending in the vertical direction;
• and
• second wordlines connected to the at least one second memory cell string and extending in the horizontal direction perpendicularly to the at least one second memory cell string, wherein the second wordlines are stacked, extend with mutually different lengths, and respectively comprise a step part and a plan part;
• and
• a row decoder between the first memory cell array and the second memory cell array, the row decoder comprising at least one wordline control line,
• wherein the at least one wordline control line is connected to the first memory cell array through a first contact, and is connected to the second memory cell array through a second contact.