Voltage level shifter

A voltage level shifter, comprising:

• a main level shifter, configured to shift an input signal within a first voltage range to an output signal within a second voltage range, wherein the main level shifter comprises:
• a first N-type transistor and a second N-type transistor, wherein source terminals of the first N-type transistor and the second N-type transistor are coupled to a first reference voltage, a drain terminal of the first N-type transistor is coupled to a gate terminal of the second N-type transistor, a drain terminal of the second N-type transistor is coupled to a gate terminal of the first N-type transistor, and the drain terminal of the first N-type transistor is configured to output the output signal;
• a third N-type transistor and a fourth N-type transistor, wherein source terminals of the third N-type transistor and the fourth N-type transistor are coupled to the drain terminals of the first N-type transistor and the second N-type transistor, respectively;
• a fifth N-type transistor and a sixth N-type transistor, wherein source terminals of the fifth N-type transistor and the sixth N-type transistor are coupled to drain terminals of the third N-type transistor and the fourth N-type transistor, respectively;
• and
• a first P-type transistor and a second P-type transistor, wherein source terminals of the first P-type transistor and the second P-type transistor are coupled to a second reference voltage, drain terminals of the first P-type transistor and the second P-type transistor are coupled to drain terminals of the fifth N-type transistor and the sixth N-type transistor, respectively, and gate terminals of the first P-type transistor and the second P-type transistor are configured to receive an inverted input signal and the input signal, respectively;
• wherein the input signal and the inverted input signal have opposite logic values;
• a first bias level shifter, coupled to the main level shifter, configured to generate a first bias voltage to gate terminals of the third N-type transistor and the fourth N-type transistor according to an enable signal and a third reference voltage;
• and
• a second bias level shifter, coupled to the main level shifter and the first bias level shifter, configured to generate a second bias voltage to a gate terminal of the fifth N-type transistor and a third bias voltage to a gate terminal of the sixth N-type transistor according to the first bias voltage and the input signal.