Semiconductor memory structure
AssigneeInvention And Collaboration Laboratory Pte. Ltd.
InventorsChao-Chun Lu, Chun Shiah
Life of this patent
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Abstract
A semiconductor memory structure includes a semiconductor substrate, a plurality of DRAM (dynamic random access memory) cells, a bit line, a sense amplifier, and a local word line. The semiconductor substrate has a top surface. Each DRAM cell includes an access transistor and a storage capacitor. The bit line has a first terminal extended along the plurality of DRAM cells to a second terminal, and the bit line is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the bit line. The local word line is connected to a gate conductive region of an access transistor of a first DRAM cell in the plurality of DRAM cells. A rising time or a falling time of a voltage signal in the local word line is less than 4 ns.
Claims21
A semiconductor memory structure comprising:
- a semiconductor substrate with a top surface, a backside surface and an active region;
- a shallow trench isolation formed outside and surrounding the active region;
- a plurality of DRAM (dynamic random access memory) cells, each DRAM cell comprising an access transistor and a storage capacitor;
- a bit line formed within the shallow trench isolation, the bit line comprising a first terminal and a second terminal, and the bit line extending from the first terminal to the second terminal, and the bit line coupled to each access transistor of the plurality of DRAM cells, wherein all of the bit line is formed within the semiconductor substrate and between the top surface of the semiconductor substrate and the backside surface of the semiconductor substrate, wherein a top surface of the bit line is lower than the top surface of the semiconductor substrate, and the bit line is outside the active region;
- a sense amplifier coupled to the first terminal of the bit line;
- and
- a local word line connected to a gate conductive region of an access transistor of a first DRAM cell in the plurality of DRAM cells;
- wherein a rising time or a falling time of a voltage signal in the local word line is less than 4 ns.
A semiconductor memory structure comprising:
- a semiconductor substrate with a top surface, a backside surface and an active region;
- a shallow trench isolation formed outside and surrounding the active region;
- a plurality of DRAM cells, each DRAM cell comprising an access transistor and a storage capacitor;
- a bit line formed within the shallow trench isolation, the bit line comprising a first terminal and a second terminal, and the bit line extending from the first terminal to the second terminal, and the bit line coupled to each access transistor of the plurality of DRAM cells, wherein all of the bit line is formed within the semiconductor substrate and between the top surface of the semiconductor substrate and the backside surface of the semiconductor substrate, wherein a top surface of the bit line is lower than the top surface of the semiconductor substrate, and the bit line is outside the active region;
- a sense amplifier coupled to the first terminal of the bit line;
- and
- a local word line connected to a gate conductive region of an access transistor of a first DRAM cell in the plurality of DRAM cells;
- wherein an RC time constant for the local word line is less than 2 ns.
A semiconductor memory structure comprising:
- a semiconductor substrate with a top surface, a backside surface and an active region;
- a shallow trench isolation formed outside and surrounding the active region;
- a plurality of DRAM cells formed based on the semiconductor substrate, each DRAM cell comprising an access transistor and a storage capacitor;
- a bit line formed within the shallow trench isolation and coupled to each access transistor of the plurality of DRAM cells, the bit line comprising a first terminal and a second terminal, and the bit line extending from the first terminal to the second terminal;
- wherein the bit line is disposed under the top surface of the semiconductor substrate, wherein all of the bit line is formed within the semiconductor substrate and between the top surface of the semiconductor substrate and the backside surface of the semiconductor substrate, wherein a top surface of the bit line is lower than the top surface of the semiconductor substrate, and the bit line is outside the active region;
- a sense amplifier coupled to a first terminal of the bit line;
- and
- a voltage source electrically connected to the sense amplifier and the bit line;
- wherein a tREF of the semiconductor memory structure is more than 200 ms.
Dependencies are inferred from the claim text.