Memory structure for low temperature operation
AssigneeIntel Corporation
InventorsSagar Suthram, Abhishek Sharma, Wilfred Gomes, Pushkar Ranade, Kuljit S. Bains, Tahir Ghani, Anand Murthy
Life of this patent
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Abstract
A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power.
Claims21
A memory device comprising:
- a memory cell, including:
- a transistor with an operating temperature in a range of approximately −25 C to +25 C having a gate stack with a combination of metal and highly doped polysilicon that adjusts a work function of the gate stack to reduce a threshold voltage (Vth) from a range of approximately 300-500 mV by 100-150 mV, to result in a reduced leakage voltage for the memory cell as compared to the Vth of 300-500 mV;
- and
- a capacitor;
- and
- an access line to drive a bias voltage for the memory cell.
A system comprising:
- a memory array including memory cells having:
- a transistor with an operating temperature in a range of approximately −25 C to +25 C having a gate stack with a combination of metal and highly doped polysilicon that adjusts a work function of the gate stack to reduce a threshold voltage (Vth) from a range of approximately 300-500 mV by 100-150 mV, to result in a reduced leakage voltage for the memory cell as compared to the Vth of 300-500 mV;
- and
- a capacitor;
- and
- an access line to drive a bias voltage for selected memory cells of the memory array;
- and
- a control circuit to selectively drive voltage on the access line.
A system comprising:
- a memory array including memory cells having:
- a transistor with an operating temperature in a range of approximately −25 C to +25 C having a gate stack with a combination of metal and highly doped polysilicon that adjusts a work function of the gate stack to reduce a threshold voltage (Vth) from a range of approximately 300-500 mV by 100-150 mV, to result in a reduced leakage voltage for the memory cell as compared to the Vth of 300-500 mV;
- and
- a capacitor;
- and
- a processor device coupled to the memory array;
- and
- a cooling system to cool the memory array to the range of approximately −25 C to +25 C.
Dependencies are inferred from the claim text.