US 12,720,725 B2 · Memory devices having vertical transistors and methods for forming the same

Abstract

A semiconductor device and methods for forming the same are provided. The semiconductor device includes an array of vertical transistors. Each transistor includes a semiconductor body extending in a vertical direction, and a gate structure located adjacent to a sidewall of the semiconductor body. The gate structures of each row of vertical transistors are connected with each other and extend along a first lateral direction to form a word line. A first word line of a first row of vertical transistors is located at a first side of the semiconductor bodies of the first row of vertical transistors along a second lateral direction perpendicular to the first lateral direction; and a second word line of a second row of vertical transistors adjacent to the first row of vertical transistors is located at a second side of the semiconductor bodies of the second row of vertical transistors along the second lateral direction.

Claims20

Dependent claims

A method for forming a semiconductor device, comprising:

forming a plurality of spacers extending along a first lateral direction, each spacer vertically extending in an upper portion of a semiconductor layer;
forming a plurality of first trenches extending along the first lateral direction, each first trench vertically extending in the upper portion of the semiconductor layer and being sandwiched, along a second lateral direction, by two adjacent spacers;
forming a bottom dielectric structure located in a lower portion of each of the first trenches by depositing a dielectric material in the plurality of first trenches;
and
forming two disconnected conductive structures on the bottom dielectric structure in each first trench, the two disconnected conductive structures laterally extending along the first lateral direction, each conductive structure vertically extending along one sidewall of the corresponding first trench.

2 more elements

A method for forming an array of memory cells, comprising:

forming a plurality of first trenches extending along a first lateral direction, each first trench vertically extending in an upper portion of a semiconductor layer;
forming a plurality of spacers extending along the first lateral direction, each spacer vertically extending in the upper portion of the semiconductor layer and being sandwiched, along a second lateral direction, by two adjacent first trenches;
forming a bottom dielectric structure located in a lower portion of each of the first trenches by depositing a dielectric material in the plurality of first trenches;
and
forming two disconnected conductive structures on the bottom dielectric structure in each first trench, the two disconnected conductive structures laterally extending along the first lateral direction, each conductive structure vertically extending along one sidewall of the corresponding first trench.

2 more elements

A method for forming a semiconductor device, comprising:

forming a plurality of spacers and a plurality of first trenches in an upper portion of a semiconductor layer, each spacer and each first trench laterally extending along a first lateral direction, wherein the plurality of first trenches and the plurality of spacers are alternatively arranged along a second lateral direction;
forming a gate dielectric layer in each first trench by oxidizing sidewalls of each first trench;
forming a bottom dielectric structure located in a lower portion of each of the first trenches by depositing a dielectric material in the plurality of first trenches;
forming two disconnected conductive structures on the bottom dielectric structure in each first trench, the two disconnected conductive structures each laterally extending along the first lateral direction and vertically covering the gate dielectric layer on one sidewall of the corresponding first trench respectively;
and
removing the plurality of spacers to form a plurality of second trenches.

3 more elements

Dependencies are inferred from the claim text.

Memory devices having vertical transistors and methods for forming the same

Life of this patent

Memory devices having vertical transistors and methods for forming the same

Life of this patent

Abstract

Claims20