Photodetection device
AssigneeSony Semiconductor Solutions Corporation
InventorsYasuji Ikeda, Qing Ding, Noam Zeev Eshel
Life of this patent
Estimating the term…
Abstract
Improved image quality in photodetection devices that count pulses with a counter is disclosed. In one example, a first sensor unit generates a first pulse signal in response to incidence of photons. A second sensor unit generates a second pulse signal in response to incidence of photons. A first counter counts a count value in synchronization with one of a plurality of signals including the first and second pulse signals, and outputs a first digital signal indicating the count value and a first carry flag indicating whether or not overflow has occurred. A second counter counts a count value in synchronization with one of the first carry flag and the second pulse signal, and outputs a second digital signal indicating the count value.
Claims19
A photodetection device comprising:
- a first sensor circuit that generates a first pulse signal in response to incidence of photons;
- a second sensor circuit that generates a second pulse signal in response to incidence of photons;
- a first counter that counts a count value in synchronization with one of a plurality of signals including the first and second pulse signals, and outputs a first digital signal indicating the count value and a first carry flag indicating whether or not overflow has occurred;
- a second counter that counts a count value in synchronization with one of the first carry flag and the second pulse signal and outputs a second digital signal indicating the count value;
- a first multiplexer that selects one of the first and second pulse signals and outputs a selected signal to the first counter as a first output signal;
- and
- a second multiplexer that selects one of the first carry flag and the second pulse signal and outputs a selected one to the second counter as a second output signal, wherein
- the first counter counts in synchronization with the first output signal,
- the second counter counts in synchronization with the second output signal,
- the first multiplexer selects the first pulse signal in a case where a low illuminance mode in which illuminance does not exceed a predetermined value is set, and alternately selects the first and second pulse signals in a case where a high illuminance mode in which illuminance is higher than the predetermined value is set, and
- the second multiplexer selects the second pulse signal in a case where the low illuminance mode is set, and selects the first carry flag in a case where the high illuminance mode is set.
A photodetection device comprising:
- a first sensor circuit that generates a first pulse signal in response to incidence of photons;
- a second sensor circuit that generates a second pulse signal in response to incidence of photons;
- a first counter that counts a count value in synchronization with one of a plurality of signals including the first and second pulse signals, and outputs a first digital signal indicating the count value and a first carry flag indicating whether or not overflow has occurred;
- and
- a second counter that counts a count value in synchronization with one of the first carry flag and the second pulse signal and outputs a second digital signal indicating the count value;
- a first multiplexer that selects one of the first and second pulse signals and outputs a selected signal to the first counter as a first output signal;
- a second multiplexer that selects one of the first carry flag and the second pulse signal and outputs a selected one to the second counter as a second output signal;
- a control circuit that controls the first and second sensor circuits, wherein
- each of the first and second sensor circuits includes an avalanche photodiode, and a recharge transistor that performs recharge to return a cathode potential of the avalanche photodiode to a predetermined potential,
- the first counter counts in synchronization with the first output signal,
- the second counter counts in synchronization with the second output signal,
- the control circuit controls a count interval, which is an interval at which the recharge is performed, to one of a plurality of intervals,
- the first multiplexer selects the first pulse signal in a case where the count interval is a long interval longer than a predetermined interval, and alternately selects the first and second pulse signals in a case where the count interval is a short interval shorter than the predetermined interval, and
- the second multiplexer selects the second pulse signal in a case where the count interval is the long interval, and selects the first carry flag in a case where the count interval is the short interval.
A photodetection device comprising:
- a first sensor circuit that generates a first pulse signal in response to incidence of photons;
- a second sensor circuit that generates a second pulse signal in response to incidence of photons;
- a first counter that counts a count value in synchronization with one of a plurality of signals including the first and second pulse signals, and outputs a first digital signal indicating the count value and a first carry flag indicating whether or not overflow has occurred;
- a second counter that counts a count value in synchronization with one of the first carry flag and the second pulse signal and outputs a second digital signal indicating the count value;
- a first logic gate that outputs a result of a logic operation on the first and second pulse signals as a first operation result;
- a first multiplexer that selects one of a plurality of signals including the first pulse signal and the first operation result and outputs a selected one to the first counter as a first output signal;
- a second multiplexer that selects one of the first carry flag and the second pulse signal and outputs a selected one to the second counter as a second output signal, wherein the first counter counts in synchronization with the first output signal, and the second counter counts in synchronization with the second output signal;
- and
- a control circuit that controls the first and second sensor circuits, wherein
- each of the first and second sensor circuits includes
- an avalanche photodiode, and
- a recharge transistor that performs recharge to return a cathode potential of the avalanche photodiode to a predetermined potential,
- the control circuit controls a count interval, which is an interval at which the recharge is performed, to one of a plurality of intervals,
- the first multiplexer selects the first pulse signal in a case where the count interval is a long interval longer than a predetermined interval, and alternately selects the first and second pulse signals in a case where the count interval is a short interval shorter than the predetermined interval, and
- the second multiplexer selects the second pulse signal in a case where the count interval is the long interval, and selects the first carry flag in a case where the count interval is the short interval.
A photodetection device comprising:
- a first sensor circuit that generates a first pulse signal in response to incidence of photons;
- a second sensor circuit that generates a second pulse signal in response to incidence of photons;
- a first counter that counts a count value in synchronization with one of a plurality of signals including the first and second pulse signals, and outputs a first digital signal indicating the count value and a first carry flag indicating whether or not overflow has occurred;
- a second counter that counts a count value in synchronization with one of the first carry flag and the second pulse signal and outputs a second digital signal indicating the count value;
- a first logic gate that outputs a result of a logic operation on the first and second pulse signals as a first operation result;
- a first multiplexer that selects one of a plurality of signals including the first pulse signal and the first operation result and outputs a selected one to the first counter as a first output signal;
- a second multiplexer that selects one of the first carry flag and the second pulse signal and outputs a selected one to the second counter as a second output signal, wherein the first counter counts in synchronization with the first output signal, and the second counter counts in synchronization with the second output signal;
- and
- a third sensor circuit that generates a third pulse signal in response to incidence of photons;
- a fourth sensor circuit that generates a fourth pulse signal in response to incidence of photons;
- a second logic gate that outputs a result of a logic operation on the third and fourth pulse signals as a second operation result;
- a third logic gate that outputs a result of a logic operation on an output of each of the first and second logic gates as a third operation result;
- a third multiplexer that outputs one of a second carry flag indicating whether or not overflow has occurred, the third pulse signal, and the second operation result as a third output signal;
- a third counter that counts a count value in synchronization with the third output signal and outputs a third digital signal indicating the count value and a third carry flag indicating whether or not overflow has occurred;
- a fourth multiplexer that outputs one of the third carry flag or the fourth pulse signal as a fourth output signal;
- and
- a fourth counter that counts a count value in synchronization with the fourth output signal and outputs a fourth digital signal indicating the count value, wherein
- the first multiplexer selects one of the first pulse signal, the first operation result, and the third operation result, and
- the second counter further generates the second carry flag.
A photodetection device comprising:
- a first sensor circuit that generates a first pulse signal in response to incidence of photons;
- a second sensor circuit that generates a second pulse signal in response to incidence of photons;
- a first counter that counts a count value in synchronization with one of a plurality of signals including the first and second pulse signals, and outputs a first digital signal indicating the count value and a first carry flag indicating whether or not overflow has occurred;
- a second counter that counts a count value in synchronization with one of the first carry flag and the second pulse signal and outputs a second digital signal indicating the count value;
- a first logic gate that outputs a result of a logic operation on the first and second pulse signals as a first operation result;
- a first multiplexer that selects one of a plurality of signals including the first pulse signal and the first operation result and outputs a selected one to the first counter as a first output signal;
- and
- a second multiplexer that selects one of the first carry flag and the second pulse signal and outputs a selected one to the second counter as a second output signal, wherein
- the first counter counts in synchronization with the first output signal, and the second counter counts in synchronization with the second output signal,
- the first multiplexer selects the first pulse signal in a case where a non-addition low illuminance mode in which illuminance does not exceed a predetermined value is set, alternately selects the first pulse signal and the first operation result in a case where a non-addition high illuminance mode in which illuminance is higher than the predetermined value is set, and selects the first operation result in a case where an addition mode is set, and
- the second multiplexer selects the second pulse signal in a case where the non-addition low illuminance mode is set, selects the first carry flag in a case where the non-addition high illuminance mode is set, and selects the first carry flag in a case where the addition mode is set.
Dependencies are inferred from the claim text.