Apparatus and method for pixel binning for charge-domain CMOS TDI imaging

An image sensor comprising:

• a plurality of pixel registers arranged in a form of a matrix;
• a first binning apparatus coupled to one end of the plurality of pixel registers, the first binning apparatus comprising:
• a row of a first transfer gate coupled to a first row of a plurality of pixel registers;
• a plurality of binning registers coupled to the first transfer gate, wherein the binning registers are disposed orthogonally to the pixel registers, wherein a channel stop disposed between two adjacent columns of the plurality of pixel registers does not exist between two adjacent binning registers;
• a plurality of second transfer gates coupled to the plurality of binning registers;
• and
• a row of storage registers coupled to the plurality of second transfer gates, wherein the channel stop extends from a first end of the pixel registers to a second end of the pixel registers and through the first transfer gate, wherein the channel stop is disposed between each of the adjacent pixel registers of the plurality of pixel registers, wherein the channel stop is disposed between each gate of the second transfer gates;
• and
• a second binning apparatus coupled to the other end of the plurality of pixel registers.

A method of pixel binning, comprising:

• transferring, by a row of a first transfer gate, a row of charges from a plurality of pixel registers to a plurality of binning registers, wherein binning is enabled for n number of pixel columns;
• transferring, by one out of every n number of a plurality of second transfer gates, only a first charge from a binning register coupled to the second transfer gate to a storage register coupled to the second transfer gate while holding the rest of charges in the rest of the binning registers, wherein the binning registers are disposed orthogonally to the pixel registers, wherein a channel stop disposed between two adjacent columns of the plurality of pixel registers does not exist between two adjacent binning registers;
• storing the first charge in the storage register;
• shifting the remaining charges in the binning registers by a column;
• transferring, by the second transfer gate, only a second charge from the binning register coupled to the second transfer gate to the storage register coupled to the second transfer gate while holding the rest of charges in the rest of the binning registers, wherein the channel stop extends from a first end of the pixel registers to a second end of the pixel registers and through the first transfer gate, wherein the channel stop is disposed between each of the adjacent pixel registers of the plurality of pixel registers, wherein the channel stop is disposed between each gate of the second transfer gates;
• adding the first charge and the second charge to generate a sum of charges;
• and
• repeating the transferring and the adding until n times binning is achieved.