Clock phase management for die-to-die (D2D) interconnect

A package comprising:

• a receiver die;
• a die-to-die (D2D) interconnect link that communicatively couples a transmitter die and the receiver die;
• and
• the transmitter die, wherein the transmitter die is to:
• identify a phase of a data signal to be transmitted on a data lane of the D2D interconnect link;
• identify a phase of a clock signal to be transmitted on a clock lane of the D2D interconnect link;
• adjust the phase of the clock signal such that the phase of the clock signal is approximately 90 degrees from the phase of the data signal, wherein an amount of adjustment of the phase of the clock signal is based on a physical medium used for the interconnect link, a characteristic of the first die or the second die, a mismatch between a parameter of the clock signal and a parameter of the data signal, a data lane-to-clock lane mismatch, or clock jitter;
• and
• transmit the clock signal and the data signal on the clock lane and the data lane, respectively,
• wherein the transmitter die includes delay lock loop (DLL) circuitry and phase interpolator (PI) circuitry to adjust the phase of the clock signal.

A method to be performed by a transmitter of a die-to-die (D2D) interconnect link, wherein the method comprises:

• identifying, by the transmitter, a phase of a data signal to be transmitted on a data lane of a D2D interconnect link, wherein the D2D interconnect link couples a first die to a second die in a package, and the D2D interconnect link includes a sideband and a mainband, wherein the mainband includes a differential clock lane, a valid lane, and a cluster of data lanes, wherein the cluster of data lanes comprises the data lane;
• identifying, by the transmitter, a phase of a clock signal to be transmitted on the clock lane;
• adjusting, using a phase interpolator and a delay-locked loop (DLL) of the transmitter, the phase of the clock signal so that the phase of the clock signal is approximately 90 degrees from the phase of the data signal;
• and
• transmitting, by the transmitter, the clock signal and the data signal on the clock lane and the data lane, respectively.