Digital-to-analog converter, manufacturing method thereof, and successive approximation register analog-to-digital converter

A manufacturing method for manufacturing a capacitive digital-to-analog converter (CDAC), comprising:

• forming a control logic circuit comprising a plurality of switch groups, comprising:
• forming a plurality of first switch circuits, wherein a first terminal of each of the plurality of first switch circuits is configured to receive a source voltage through a first metal layer of the CDAC, and a control terminal of each of the plurality of first switch circuits is configured to receive one of a plurality of turn-on signals through a second metal layer of the CDAC;
• and
• forming a plurality of second switch circuits, wherein a first terminal of each of the plurality of second switch circuits is configured to receive a ground voltage through the first metal layer, and a control terminal of each of the plurality of second switch circuits is configured to receive another of the plurality of turn-on signals through the second metal layer;
• and
• forming a capacitive structure, wherein the capacitive structure is located at least in a third metal layer of the CDAC and coupled to a plurality of second terminals of the plurality of first switch circuits and the plurality of second switch circuits through a plurality of first vias extending along a vertical direction,
• wherein in the vertical direction, the third metal layer is located above the first metal layer and the second metal layer, and the vertical direction is vertical to plane directions of the first metal layer, the second metal layer and the third metal layer.

A successive approximation register analog-to-digital converter (SAR ADC), comprising:

• a capacitive digital-to-analog converter (CDAC), comprising a capacitive structure and a control logic circuit coupled to each other, configured to sample an input signal and generating a first signal and a second signal, and the control logic circuit is configured to adjust the first signal and the second signal based on a plurality of turn-on signals;
• a comparator, coupled to the CDAC and configured to generate a decision signal based on the first signal and the second signal;
• and
• a logic decision circuit, coupled to the CDAC and the comparator, and configured to generate the plurality of turn-on signals and an output signal based on the decision signal,
• wherein the control logic circuit is configured to receive a source voltage and a ground voltage through a first metal layer of the CDAC, configured to be coupled to the capacitive structure through a plurality of first vias of the CDAC extending along a vertical direction, and configured to receive the plurality of turn-on signals through a second metal layer of the CDAC, the capacitive structure is located at least in a third metal layer of the CDAC, and
• in the vertical direction, the third metal layer is located above the first metal layer and the second metal layer, wherein the vertical direction is vertical to plane directions of the first metal layer, the second metal layer and the third metal layer.