US 12,719,489 B2 · Semiconductor integrated circuit, receiving device, and receiving method

Abstract

In general, according to one embodiment, a semiconductor integrated circuit includes the following configuration. A first converter samples a first digital value from an analog signal based on a first clock signal. A second converter samples a second digital value from the analog signal based on a second clock signal differing from the first clock signal by a first phase. A first processing circuit calculates phase shifts of the first and second clock signals based on the first and second digital values and using a first frequency of a third clock signal. A second processing circuit generates a control signal for correcting the phase shifts of the first and second clock signals based on the phase shifts calculated by the first processing circuit and using a second frequency of a fourth clock signal. The second frequency is 2m times the first frequency.

Claims18

Dependent claims

A semiconductor integrated circuit comprising:

a first converter configured to sample a first digital value from an analog signal based on a first clock signal;
a second converter configured to sample a second digital value from the analog signal based on a second clock signal differing from the first clock signal by a first phase;
a first processing circuit configured to calculate a phase shift of the first clock signal and the second clock signal based on the first digital value and the second digital value and using a first frequency of a third clock signal as an operating frequency;
and
a second processing circuit configured to generate a control signal for correcting the phase shift of the first clock signal and the second clock signal based on the phase shift calculated by the first processing circuit and using a second frequency of a fourth clock signal as an operating frequency, the second frequency being 2m times the first frequency, where m is an integer equal to or greater than 1.

2 more elements

A receiving method comprising:

sampling a first digital value from an analog signal based on a first clock signal;
sampling a second digital value from the analog signal based on a second clock signal differing from the first clock signal by a first phase;
calculating a phase shift of the first clock signal and the second clock signal based on the first digital value and the second digital value and using a first frequency of a third clock signal as an operating frequency;
and
generating a control signal for correcting the phase shift of the first clock signal and the second clock signal based on the calculated phase shift and using a second frequency of a fourth clock signal as an operating frequency, the second frequency being 2m times the first frequency, where m is an integer equal to or greater than 1.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit, receiving device, and receiving method

Life of this patent

Semiconductor integrated circuit, receiving device, and receiving method

Life of this patent

Abstract

Claims18