Amplifier circuit
AssigneesDenso Corporation, Toyota Jidosha Kabushiki Kaisha, MIRISE Technologies Corporation
InventorsShotaro Wada, Tomohiro Nezuka, Yoshikazu Furuta
Life of this patent
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Abstract
An amplifier circuit includes: an amplifier; a first switched resistor unit configured by connecting in series a first resistance element having one or more resistors and a first switch, and having one end connected to an input terminal of the amplifier; a second resistance element unit connected between an other end of the first switched resistor unit and an output terminal of the amplifier and including one or more resistors; a second switch connected between a common connection point of the first switched resistor unit and the second resistance element unit and a reset potential point; and a control circuit for exclusively turning on and off the first switch and the second switch, respectively.
Claims4
An amplifier circuit comprising:
- an amplifier;
- a first switched resistor unit configured by connecting in series a first resistance element having one or more resistors and a first switch, and having one end connected to an input terminal of the amplifier;
- a second resistance element unit connected between an other end of the first switched resistor unit and an output terminal of the amplifier and including one or more resistors;
- a second switch connected between a common connection point of the first switched resistor unit and the second resistance element unit and a reset potential point;
- a control circuit for exclusively turning on and off the first switch and the second switch, respectively;
- and
- a third switch arranged on an output terminal side of the amplifier from the first switch, and connected in series with the first switched resistor unit and the second resistance element unit, or in series with the first switched resistor unit or the second resistance element unit, wherein:
- the control circuit delays an on and off timing of the third switch from an on and off timing of the first switch within a delay range in which an on-state period of the third switch overlaps an on-state period of the first switch.
Dependencies are inferred from the claim text.