Low noise amplifier with post distortion circuit

An improvement for an RF amplifier circuit operating within a range of frequencies having a low noise amplifier producing RF signals on an output and a load coupled to the output to receive the RF signals, the improvement comprising:

• a post distortion (PD) circuit having a semiconductor device with a control gate biased to cause the semiconductor device to operate in a nonlinear region at or near pinch-off, wherein active devices in the semiconductor device are high electron mobility transistors (HEMT) having indium arsenide composite channel (IACC) technology;
• the PD circuit having a PD port that is coupled to the output of the low noise amplifier;
• the PD circuit generating at least one PD intermodulation product at the PD port in response to the RF signals being received from the low noise amplifier through a coupling by the PD circuit, the at least one PD intermodulation product being out of phase to an intermodulation product produced by the low noise amplifier that is present at the output;
• and
• the at least one PD intermodulation product combining with the intermodulation product produced by the low noise amplifier to cause a reduction of the intermodulation product at the load by at least 10 dB for at least one frequency in the range of frequencies, wherein the low noise amplifier comprises first and second transistors operating as a dual gate device, wherein a bias circuit causes a DC quiescent voltage across the gate of the first transistor to be 30% to 40% of a total gate voltage across both transistors to reduce a second order intermodulation product.

An RF amplifier circuit operating within a range of frequencies comprising:

• a low noise amplifier producing RF signals including a second order intermodulation product on an output;
• a load coupled to the output to receive the RF signals and second order intermodulation product;
• the low noise amplifier having first and second transistors operating as a dual gate device;
• a bias circuit coupled to the first and second transistors establishes a DC quiescent voltage across each of the first and second transistors with the sum of the DC quiescent voltages across the first and second transistors being a total voltage;
• the bias circuit causing the DC quiescent voltage across the first transistor to be 30% to 40% of the total voltage and the DC quiescent voltage across the second transistor to be 70%-60%, respectively, of the total voltage;
• and
• the unequal DC quiescent voltages across the first and second transistors causing a reduction of the second intermodulation product produced by the first and second transistors as compared with a second intermodulation product produced by the first and second transistors operating with equal DC quiescent voltages across the first and second transistors.