High speed amplifier circuit

An N-phase high-speed amplifier circuit comprising

• a plurality of high-speed amplifier circuits configured to perform N phases of level conversions on a differential signal,
• wherein each of the plurality of high-speed amplifier circuits comprises:
• a first bias conversion circuit;
• a second bias conversion circuit;
• a first transmission circuit electrically connected to the first bias conversion circuit and configured to output a first differential signal having a voltage of a level within a first range among all levels, based on the differential signal on which a level-down operation is performed by the first bias conversion circuit;
• and
• a second transmission circuit electrically connected to the second bias conversion circuit and configured to output a second differential signal having a voltage of a level within a second range among all the levels, based on the differential signal on which a level-up operation is performed by the second bias conversion circuit, and
• the first differential signal and the second differential signal output from an N-m-1th-phase high-speed amplifier circuit among the plurality of high-speed amplifier circuits are respectively input to a first bias conversion circuit and a second bias conversion circuit of an N-mth-phase high-speed amplifier circuit, where m is an integer of at least 0 but not more than N−2.

An electronic device comprising:

• a communication interface;
• a plurality of input circuits configured to receive a differential signal from the communication interface;
• a high-speed amplifier circuit electrically connected to the plurality of input circuits;
• and
• at least one processor configured to apply a preset voltage or current to the high-speed amplifier circuit,
• wherein the high-speed amplifier circuit comprises:
• a first bias conversion circuit configured to perform a level-down operation on a positive differential signal input via a first input circuit among the plurality of input circuits;
• a second bias conversion circuit configured to perform a level-up operation on a negative differential signal input via a second input circuit among the plurality of input circuits;
• a first transmission circuit electrically connected to the first bias conversion circuit and configured to output a first differential signal having a voltage of a level within a first range among all levels, based on the positive differential signal on which the level-down operation has been performed;
• and
• a second transmission circuit electrically connected to the second bias conversion circuit and configured to output a second differential signal having a voltage of a level within a second range among all the levels, based on the negative differential signal on which the level-up operation has been performed.