Data receiving circuit, data receiving system and storage apparatus

A data receiving circuit, comprising:

• a first amplification circuit, configured to receive a data signal, a first reference signal and a second reference signal, perform first comparison on the data signal and the first reference signal to output a first signal pair as a result of the first comparison, and perform second comparison on the data signal and the second reference signal to output a second signal pair as a result of the second comparison, wherein a level value of the first reference signal is different from a level value of the second reference signal, the first signal pair comprises a first signal and a second signal, and the second signal pair comprises a third signal and a fourth signal;
• a decision equalization enable circuit, configured to receive an enable signal and a feedback signal, and output a control signal, wherein the feedback signal is obtained based on previously received data, the enable signal has a first level value period, a level value of the control signal varies with a level value of the feedback signal, the enable signal has a second level value period, the level value of the control signal is a fixed value, and a first level value is different from a second level value;
• and
• a second amplification circuit, configured to selectively receive the first signal pair or the second signal pair as an input signal pair based on the control signal, amplify a voltage difference of the input signal pair, and output a first output signal and a second output signal as a result of the amplification;
• wherein the second amplification circuit comprises:
• a first input circuit, connected to a seventh node and an eighth node, and configured to be turned on in response to the control signal to receive the first signal pair and perform a third comparison, and provide a signal to the seventh node and the eighth node respectively as a result of the third comparison;
• a second input circuit, connected to the seventh node and the eighth node, and configured to be turned on in response to the control signal to receive the second signal pair and perform a fourth comparison, and provide a signal to the seventh node and the eighth node respectively as a result of the fourth comparison, wherein
• the first input circuit and the second input circuit are alternatively turned on based on the control signal;
• and
• a latch circuit, connected to the seventh node and the eighth node, and configured to amplify and latch the signal of the seventh node and the signal of the eighth node, and output the first output signal and the second output signal via a first output node and a second output node;
• wherein the feedback signal comprises a differential first feedback signal and second feedback signal;
• the control signal comprises a differential first control signal and second control signal;
• the first input circuit is turned on in response to the first control signal, and the second input circuit is turned on in response to the second control signal;
• and the decision equalization enable circuit comprises:
• a first enable circuit, configured to receive the enable signal and the feedback signal, and output the first control signal, wherein the enable signal has the first level value period, a level value of the first control signal varies with a level value of the first feedback signal, the enable signal has the second level value period, and the level value of the first control signal is a fixed value;
• and
• a second enable circuit, configured to receive a complementary enable signal and the second feedback signal, and output the second control signal, wherein the complementary enable signal and the enable signal are differential signals for each other, the complementary enable signal has the second level value period, a level value of the second control signal varies with a level value of the second feedback signal, the complementary enable signal has the first level value period, and the level value of the second control signal is a fixed value.