Drain-ballasted electrostatic discharge protection circuits

A system comprising:

• a first voltage domain including a first FinFET transistor configured to operate at a first supply voltage;
• a second voltage domain including second FinFET transistor configured to operate at a second supply voltage;
• and
• a drain-ballasted electrostatic discharge (ESD) protection circuit configured to electrically coupled to the first voltage domain and the second voltage domain, the drain-ballasted ESD protection circuit comprising:
• a first NMOS transistor;
• a second NMOS transistor in series with the first NMOS transistor;
• a floating interconnect configured to electrically couple the first NMOS transistor to the second NMOS transistor;
• and
• a resistor directly coupled to a first gate of the first NMOS transistor, a second gate of the second NMOS transistor, and to ground.

A memory device, comprising:

• a first voltage domain including:
• a first power pin configured to supply a first supply voltage;
• a first ground pin;
• and
• a first FinFET electrically coupled to the first power pin and the first ground pin,
• wherein the first FinFET is configured to operate at the first supply voltage;
• a second voltage domain including:
• a second power pin configured to supply a second supply voltage that is higher than the first supply voltage;
• a second ground pin;
• and
• a second FinFET electrically coupled to the second power pin and the second ground pin, wherein the second FinFET is configured to operate at the second supply voltage;
• and
• a bi-directional drain-ballasted electrostatic discharge (ESD) protection circuit configured to electrically couple the first voltage domain and the second voltage domain responsive to a detection of an ESD event, the bi-directional drain-ballasted ESD circuit comprising:
• a first NMOS transistor including a first source, a first drain, and a first gate;
• a second NMOS transistor including a second source, a second drain, and a second gate;
• a floating interconnect configured to electrically couple the first source of the first NMOS transistor to the second source of the second NMOS transistor;
• and
• a grounding resistor directly electrically coupled to the first gate, the second gate, and ground.