ESD protection circuit
AssigneeLAPIS Technology Co., Ltd.
InventorSatoru Kurotsu
Life of this patent
Estimating the term…
Abstract
An RC circuit 110 is connected in series between VDD and GND. A RC circuit 120 is set with a time constant different from that of the RC circuit 110 connected in series between VDD and GND. In the inverter circuit 210, a potential is input between a resistance element 111 and a capacitance element 112. In the inverter circuit 220, a potential is input between a resistance element 121 and a capacitance element 122. In an NMOS transistor 310, an output of the inverter circuit 210 is input to a gate terminal, and a drain terminal is connected to VDD. In an NMOS transistor 320, an output of the inverter circuit 220 is input to a gate terminal, a drain terminal is connected with a source terminal of the NMOS transistor 310, and a source terminal is connected with GND.
Claims12
An ESD protection circuit, comprising:
- a first RC circuit, connected in series between a power wiring and a ground wiring;
- a first inverter circuit, to which a potential between a resistance element and a capacitance element forming the first RC circuit is input, and which is connected between the power wiring and the ground wiring;
- a second RC circuit, which is connected in series between the power wiring and the ground wiring, and in which a time constant different from that of the first RC circuit is set;
- a second inverter circuit, to which a potential between a resistance element and a capacitance element forming the second RC circuit is input, and which is connected between the power wiring and the ground wiring;
- a first NMOS transistor, in which an output of the first inverter circuit is input to a gate terminal, and a drain terminal is connected with the power wiring;
- and
- a second NMOS transistor, in which an output of the second inverter circuit is input to a gate terminal, a drain terminal is connected with a source terminal of the first NMOS transistor, and a source terminal is connected with the ground wiring.
An ESD protection circuit, comprising:
- a first CR circuit, connected in series between a power wiring and a ground wiring;
- a first inverter circuit, to which a potential between a capacitance element and a resistance element forming the first CR circuit is input, and which is connected between the power wiring and the ground wiring;
- a second CR circuit, which is connected in series between the power wiring and the ground wiring, and in which a time constant different from that of the first CR circuit is set;
- a second inverter circuit, to which a potential between a capacitance element and a resistance element forming the second CR circuit is input, and which is connected between the power wiring and the ground wiring;
- a first PMOS transistor, in which an output of the first inverter circuit is input to a gate terminal, and a source terminal is connected with the power wiring;
- and
- a second PMOS transistor, in which an output of the second inverter circuit is input to a gate terminal, a source terminal is connected with a drain terminal of the first PMOS transistor, and a drain terminal is connected with the ground wiring.
Dependencies are inferred from the claim text.