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US 12,719,145 B2Granted
Apparatus comprising delay lines formed on a first metal layer via connected to delay lines formed on a second metal layer in a particular arrangement
AssigneeTexas Instruments Incorporated
InventorsKarthikeyan Gunasekaran, Jagannathan Venkataraman, Raviprasad Kuloor, Sharanaprasad Melkundi, Yokesh Pari, Eeshan Miglani
Life of this patent
Estimating the term…
Abstract
An example apparatus includes: a first metal layer including: a first delay line having a surface area; and a second metal layer including: a second delay line having a surface area overlapping the surface area of the first delay line; and an insulating layer coupled between the first metal layer and the second metal layer.
Claims18
An integrated circuit comprising:
- a first metal layer including a first delay line and a second delay line, the first delay line having a surface area;
- a second metal layer including a third delay line and a fourth delay line, the third delay line having a surface area overlapping the surface area of the first delay line;
- an insulating layer between the first metal layer and the second metal layer
- a first via coupled to the first delay line and the fourth delay line through the insulating layer;
- and
- a second via coupled to the second delay line and the third delay line through the insulating layer.
3 more elements
An apparatus comprising:
- a first layer including a first waveguide and a second waveguide, the first waveguide having a surface;
- a second layer including a third waveguide and a fourth waveguide, the third waveguide having a surface overlapping the surface of the first waveguide;
- a third layer between the first layer and the second layer
- a first via coupled to the first waveguide and the fourth waveguide through the third layer, the first waveguide, the fourth waveguide, and the first via structured as first delay circuitry;
- and
- a second via coupled to the second waveguide and the third waveguide through the third layer, the second waveguide, the third waveguide, and the second via structured as second delay circuitry.
3 more elements
An apparatus comprising:
- a first layer including a first electrical trace having a surface area;
- and
- a second layer including a second electrical trace having a surface area overlapping the surface area of the first electrical trace;
- a third layer coupled between the first layer and the second layer;
- a first analog-to-digital converter (ADC) coupled to the first electrical trace and the second electrical trace;
- and
- a second ADC coupled to the first ADC by at least one of the first electrical trace or the second electrical trace.
4 more elements
Dependencies are inferred from the claim text.