NAND detect program completion (NDPC) with power off charge loss calibration in a memory sub-system
AssigneeMicron Technology, Inc.
InventorsPeng Zhang, Lei Lin, Zhengang Chen, Murong Lang, Zhenming Zhou
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AssigneeMicron Technology, Inc.
InventorsPeng Zhang, Lei Lin, Zhengang Chen, Murong Lang, Zhenming Zhou
Estimating the term…
A system including a memory device and an operatively coupled processing device to perform operations including: responsive to detecting a power-up event, performing a first read strobe on a first set of a plurality of memory cells addressable by a first wordline, determining a value of a conductivity metric reflecting conductive states of one or more bitlines connected to the first set of the plurality of memory cells, determining, based on the value of the conductivity metric, a read level offset value for a second wordline, wherein the second wordline is adjacent to the first wordline, performing, using the read level offset value, a second read strobe on the second wordline, and responsive to determining that a value of a quality metric produced by the second read strobe satisfies a quality criterion, indicating that a programming operation performed on the second wordline was completed before a power off event.
A system comprising:
A method comprising:
A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a controller managing a memory device comprising a plurality of memory cells, cause the controller to:
Dependencies are inferred from the claim text.