Memory device, memory system, memory controller and operating method thereof

A memory system, including:

• one or more memory devices, comprising:
• an array of memory cells including a memory cell with multiple storage bits;
• wherein a preset number of the memory cells form at least one code word, and the multiple storage bits correspond to multiple pages respectively;
• wherein at least one page of the multiple pages corresponds to multiple stages;
• wherein the multiple stages include a first stage and a second stage;
• and wherein each of the multiple stages corresponds to a respective read voltage, and the read voltage corresponding to the second stage is less than the read voltage corresponding to the first stage;
• a peripheral circuit coupled to the array of memory cells and configured to:
• obtain a target valley voltage in a first target stage, the first target stage including at least one first stage among multiple first stages corresponding to the multiple pages;
• and determine the read voltage at which a read operation is performed on the at least one code word based on the target valley voltage;
• and
• obtain a predicted valley voltage in a second target stage in accordance with the target valley voltage in the first target stage, the second target stage including at least one of remaining first stages or the second stage;
• wherein the read voltage corresponding to the second target stage is less than the read voltage corresponding to the first target stage;
• and
• a memory controller coupled to the memory device and controlling the memory device.

A memory controller coupled to at least one memory device, the memory controller comprising:

• a control component configured to:
• obtain a target valley voltage in a first target stage, the first target stage including at least one first stage among multiple first stages corresponding to multiple pages in the memory device;
• and determine a read voltage at which a read operation is performed on at least one code word based on the target valley voltage;
• wherein the memory device includes memory cells including a memory cell with multiple storage bits, a preset number of the memory cells form the at least one code word, and the multiple storage bits correspond to multiple pages respectively;
• and wherein at least one page corresponds to multiple stages, the multiple stages include a first stage and a second stage, and wherein each of the multiple stages corresponds to a respective read voltage, and the read voltage corresponding to the second stage is less than the read voltage corresponding to the first stage;
• and
• obtain a predicted valley voltage in a second target stage in accordance with the target valley voltage in the first target stage;
• the second target stage including at least one of remaining first stages or the second stage;
• wherein the read voltage corresponding to the second target stage is less than the read voltage corresponding to the first target stage.